Cache Coherency Protocol for Partial Read Ordering
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Solution Overview
Problem
Current cache coherency protocols face challenges in maintaining data integrity and system stability due to conflicts arising from partial reads and non-snoop memory accesses, which can lead to the forwarding of invalid data, causing instability and illegal operations in multi-cache systems.
Innovation Solution
The implementation of a protocol architecture that ensures proper memory ordering through messaging protocols, such as the MESIF protocol, which uses point-to-point interconnects to maintain data consistency and resolve conflicts by invalidating cached copies before forwarding data, ensuring that only valid data is accessed and used within the system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If partial reads and non-snoop memory accesses are allowed in cache coherency protocols, then system performance and flexibility are improved, but data integrity and system stability deteriorate due to potential forwarding of invalid data
Solution Approach 1:
The protocol performs preliminary validation checks before forwarding data. Specifically, it checks whether a cached copy is valid before allowing a partial read to forward data, and validates memory ordering before allowing non-snoop accesses to proceed. This preliminary validation prevents invalid data from being forwarded while still allowing these access types to improve system performance.
Solution Approach 2:
The protocol introduces an intermediary validation mechanism between the memory access request and the data forwarding action. This intermediary layer checks memory ordering requirements and cached copy validity, acting as a mediator that allows partial reads and non-snoop accesses to proceed only when they will not compromise data integrity.
2Quantity of substance
If multiple cache memories are used to increase system capacity, then data storage capability is improved, but coherency maintenance complexity increases leading to more conflicts
Solution Approach 1:
The coherency protocol is segmented into distinct validation stages: checking if the accessed address is cached, validating the cached copy's validity, checking memory ordering requirements, and then allowing the access to proceed. This segmentation of the coherency maintenance process into manageable stages reduces the overall complexity of managing multiple cache memories.
3Device complexity
If a single component is responsible for conflict resolution in cache coherency protocols, then protocol simplicity is maintained, but overall system performance decreases
Solution Approach 1:
The protocol enables each cache memory component to independently validate its own cached copies and make local decisions about whether to forward data or allow access. This self-service approach eliminates the need for a centralized conflict resolution component, maintaining protocol simplicity while improving system performance through distributed decision-making.
Data Source
AI summary
A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.