Multi-core Cache Coherency Verification via Primary-Secondary Pattern Matching
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Solution Overview
Problem
The deployment of multi-core processors with cache coherency mechanisms in safety-critical avionics environments poses challenges in verifying the proper operation of hardware-based cache coherency, which is crucial for ensuring system reliability and safety.
Innovation Solution
A processor system and method that designates a primary core and secondary cores to test cache coherency by generating and comparing translation lookaside buffer mappings, locking cache lines, and performing data pattern updates and flushes to verify coherence, with the primary core logging fatal faults if mismatches occur, and switching core statuses in a round-robin manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-core cache coherency mechanism is deployed in safety-critical avionics environment, then processing capability is improved, but verification difficulty increases
Solution Approach 1:
The patent creates test copies of cache lines and data patterns to verify coherency. The primary core generates test data patterns and writes them to cache lines, then these patterns are copied/propagated to secondary cores through the cache coherency mechanism. By comparing the copied data at secondary cores with the original test patterns, the system can verify whether the cache coherency mechanism is functioning correctly without requiring complex external verification equipment.
2Reliability
If comprehensive cache coherency verification is performed, then system reliability is improved, but test complexity increases
Solution Approach 1:
The cache coherency verification system is self-testing, meaning the processor cores themselves generate and execute the test sequences. The primary core generates test data patterns, writes them to cache lines, and initiates the coherency verification process. Secondary cores receive notifications and automatically compare their cached data with the test patterns. This self-service approach eliminates the need for external test equipment and complex test orchestration, reducing test complexity while maintaining comprehensive verification.
Solution Approach 2:
The patent focuses verification on specific cache lines and data patterns rather than attempting to verify every possible state transition. The primary core selects particular cache lines to lock and update with specific test patterns, performing a targeted verification that is sufficient to detect coherency failures without exhaustively testing all possible scenarios. This partial action approach maintains reliability while reducing test complexity.
3Measurement precision
If cache line locking and flushing operations are performed, then coherency verification accuracy is improved, but processing overhead increases
Solution Approach 1:
The primary core performs preliminary actions by pre-locking the cache lines that will be used for testing before the actual verification begins. It also pre-generates the test data patterns and prepares the cache coherency mechanism in advance. This preliminary setup ensures that when the actual verification occurs, the cache lines are already in the correct state and the test patterns are ready, eliminating the need for repeated locking and flushing operations during the verification process, thus reducing processing overhead while maintaining accuracy.
Data Source
AI summary
A system and method for verifying cache coherency in a safety-critical avionics processing environment includes a multi-core processor (MCP) having multiple cores, each core having at least an L1 data cache. The MCP may include a shared L2 cache. The MCP may designate one core as primary and the remainder as secondary. The primary core and secondary cores create valid TLB mappings to a data page in system memory and lock L1 cache lines in their data caches. The primary core locks an L2 cache line in the shared cache and updates its locked L1 cache line. When notified of the update, the secondary cores check the test pattern received from the primary core with the updated test pattern in their own L1 cache lines. If the patterns match, the test passes; the MCP may continue the testing process by updating the primary and secondary statuses of each core.