Cache Coherency Handling for Self-Modifying Code
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern microprocessors with separate instruction and data caches face challenges in handling cache coherency for self-modifying code, particularly due to the difficulty of the program-store-compare (PSC) bus timing path and its resource-intensive nature, which can harm system performance by requiring postponement of normal cache invalidate handling.
Innovation Solution
A method is introduced where a PSC tag is allocated by the load-store unit and sent to coherency logic, along with an exclusive fetch for the cache line, and an invalidation request is sent to the instruction cache with a PSC indicator, allowing for a fast-path check against an instruction address table to determine if prefetched instructions need to be discarded, eliminating the need for a dedicated PSC bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated PSC bus is used to detect stores into instruction storage, then cache coherency for self-modifying code is ensured, but wiring resources are significantly consumed and timing path becomes difficult
Solution Approach 1:
The patent combines the PSC detection function with the existing cache invalidation mechanism. The data cache uses the same invalidation pathway to detect and handle stores to instruction storage, eliminating the need for a separate PSC bus. The coherency logic that normally handles cache invalidation now also performs PSC detection by checking if the store address matches prefetched instruction addresses.
Solution Approach 2:
The cache invalidation mechanism is given multiple functions: it continues to handle normal cache invalidation operations while also performing PSC detection. The coherency logic serves dual purposes by managing both cache coherence protocol and PSC checking, reducing the need for dedicated hardware resources.
2Reliability
If PSC checks are performed through a dedicated bus, then instruction address matching is detected, but normal cache invalidate handling must be postponed which harms system performance
Solution Approach 1:
The patent merges PSC detection with the cache invalidation pathway, allowing both operations to proceed through the same hardware structures without requiring sequential processing. The coherency logic processes both cache invalidation requests and PSC detection simultaneously using the same address comparison mechanisms.
Solution Approach 2:
The instruction cache maintains a table of prefetched instruction addresses in advance. When a store operation occurs, the address is immediately compared against this pre-maintained table, enabling fast PSC detection without requiring complex real-time analysis or postponing other operations.
3Device complexity
If the data cache lacks information about instruction storage, then separate instruction and data cache design is simplified, but the data cache cannot determine whether modified data affects instruction storage
Solution Approach 1:
The patent introduces coherency logic as an intermediary between the data cache and instruction cache. This intermediary component receives store addresses from the data cache, checks them against the prefetched instruction address table, and triggers invalidation of affected instruction cache lines. The data cache itself remains simple without needing to know about instruction storage.
Solution Approach 2:
The instruction cache performs self-service by maintaining its own table of prefetched addresses and autonomously detecting when stores to its content occur. The instruction cache receives store addresses and independently determines which of its lines need invalidation without requiring complex communication with the data cache.
Data Source
AI summary
A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.