Multi-Level Cache Coherency with Silent Dirty-Line Eviction
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Solution Overview
Problem
Existing multi-level cache systems struggle to effectively address coherency issues in maintaining coherency across subsystems, particularly those involving existing subsystems, particularly those involving existing subsystems, specifically those involving existing subsystems, such as cache coherency management in multi-level cache systems, where maintaining coherency while adhering to non-inclusive non-exclusive (NINE) policies is challenging, especially in systems with greater than two processors.
Innovation Solution
A method and system for cache coherency management in multi-level cache systems that involves selecting a victim line for eviction from a lower-level cache, writing the data to a higher-level cache silently without notification, and maintaining cache coherency by ensuring the system remains faithful to the NINE policy, using cache maintenance operations like CleanShared instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cache coherency protocols are used in multi-level cache systems, then coherency can be maintained, but the number of transactions and system complexity increase significantly
Solution Approach 1:
The patent extracts the coherency management function from the traditional cache system by introducing a separate translation lookup buffer (TLB) that operates independently. The TLB handles address translation and coherency tracking separately from the cache data operations, allowing the cache system to maintain coherency without complex inter-cache communication protocols.
Solution Approach 2:
The patent introduces a TLB as an intermediary component between the processor and the multi-level cache system. This TLB acts as a mediator that tracks address translations and manages coherency information, reducing the need for direct coherency management between multiple cache levels and thereby reducing overall system complexity.
2Reliability
If inclusive cache policies are used to maintain coherency, then coherency is easier to maintain, but space utilization decreases due to redundant storage
Solution Approach 1:
The patent uses selective copying of only the necessary coherency information into the TLB rather than maintaining full copies of cache data across all levels. The TLB stores translation entries and coherency metadata that reference the actual data locations, allowing coherency to be tracked without duplicating the entire data set across multiple cache levels.
Solution Approach 2:
The patent moves coherency management from the vertical dimension (across cache levels) to the horizontal dimension (within the TLB at a single level). By managing coherency information in the TLB alongside address translations, the system maintains coherency without requiring vertical synchronization between multiple cache levels, thereby improving space utilization.
3Quantity of substance
If non-inclusive non-exclusive (NINE) policies are implemented, then space utilization improves, but coherency management becomes more difficult
Solution Approach 1:
The patent enables the TLB to self-manage coherency information for NINE policies. When cache lines are allocated or evicted, the TLB automatically updates its translation entries and coherency tracking information without requiring complex coordination between cache levels. This self-service approach to coherency management simplifies the implementation of NINE policies while maintaining space efficiency.
Solution Approach 2:
The patent implements feedback mechanisms in the TLB that track the state of cache lines and provide information about coherency status. The TLB monitors cache allocations and evictions, and uses this feedback to maintain accurate translation and coherency information, enabling NINE policies to operate correctly without increasing overall system complexity.
4Reliability
If cache maintenance operations are performed frequently to maintain coherency, then coherency is maintained, but processing performance decreases due to operation overhead
Solution Approach 1:
The patent performs preliminary coherency management by maintaining translation and coherency information in the TLB before cache operations occur. When address translations are needed, the TLB already has the coherency status information ready, eliminating the need for frequent cache maintenance operations during data access and thereby preserving processing performance.
Solution Approach 2:
The patent allows the system to skip unnecessary cache maintenance operations by using the TLB's coherency information. When the TLB indicates that coherency is already maintained or that no coherency action is needed, the system can proceed directly with data access without performing expensive cache maintenance operations, thus improving processing performance.
Data Source
AI summary
A method for cache coherency management in multi-level cache systems includes, for occurrence of a conflict eviction from a set of a cache at a first level from the multi-level coherent system, selecting a victim line from the set of the cache for eviction. For the victim line being dirty and a second level from the multi-level coherent system having a copy of the victim line, the method includes writing data to a third level from the multi-level coherent system using a cache maintenance operation, and silently dropping the victim line without notification to the third level. The second level is a level directly lower than the first level, and the third level is a level directly higher than the first level.