Cache Coherency Control for Speculative Read Security
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Solution Overview
Problem
Modern processors' speculative execution and caching mechanisms can be exploited by attackers to infer sensitive information through cache timing side-channels, even when speculative read operations are cancelled, as changes in coherency states in other caches can persist and reveal accessed addresses.
Innovation Solution
Implementing a safe-speculative-read transaction that prohibits changes in coherency states in other caches, allowing speculative reads without triggering state changes, and using non-cacheable or cacheable read responses to manage data access and ensure security, while also training data prefetchers to predict addresses based on resolved operations to prevent eviction of non-speculative data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If speculative read operations are permitted to improve execution speed, then processing throughput is improved, but security is worsened due to cache timing side-channel attacks
Solution Approach 1:
The cache is segmented into a first cache and a second cache. The first cache stores data accessible by a first process, while the second cache stores data accessible by a second process. This segmentation prevents speculative read operations from one process from affecting the coherency state of data in the other cache, thereby eliminating the security vulnerability while maintaining speculative execution for performance improvement.
Solution Approach 2:
A coherency control mechanism acts as an intermediary between the first cache and the second cache. When a speculative read operation is detected, the coherency control prevents the operation from triggering a change in coherency state in the second cache. This intermediary control allows speculative execution to proceed for performance while blocking the security attack vector.
2Reliability
If coherency state changes are permitted in other caches to maintain cache coherence, then data consistency is improved, but information leakage is worsened through cache timing side-channels
Solution Approach 1:
The cache system is segmented into process-specific cache regions. The first cache is associated with the first process and the second cache with the second process. This segmentation ensures that coherency state changes in one cache do not affect the other, preventing information leakage through cache timing side-channels while maintaining data consistency within each process's cache.
Solution Approach 2:
Different coherency management policies are applied to different cache regions based on local security requirements. The first cache allows coherency state changes for the first process, while the second cache is protected from coherency state changes triggered by speculative operations from the first process. This local quality approach maintains data consistency where needed while preventing information leakage.
3Object-affected harmful factors
If speculative reads are blocked to prevent security attacks, then security is improved, but processing performance is worsened
Solution Approach 1:
The cache is segmented into process-specific regions, allowing speculative read operations to proceed within the security boundaries of each process's cache. This segmentation provides security protection by preventing cross-process speculative access while maintaining processing performance by allowing speculative execution to continue within authorized cache regions.
4Productivity
If a single cache is used to improve cache hit rate, then cache efficiency is improved, but security is worsened due to cross-process interference
Solution Approach 1:
The cache is segmented into a first cache and a second cache, with each cache dedicated to a specific process. This segmentation eliminates cross-process interference and security vulnerabilities while maintaining cache efficiency. Each process benefits from dedicated cache space, and the overall system achieves security without sacrificing cache hit rates for authorized accesses.
Data Source
Figure 1
Figure 2A~2B
Figure 3
AI summary
Coherency control circuitry 10 supports processing of a safe-speculative-read transaction received from a requesting master device 4. The safe-speculative-read transaction is of a type requesting that target data is returned to a requesting cache 11 of the requesting master device 4 while prohibiting any change in coherency state associated with the target data in other caches 12 in response to the safe-speculative-read transaction. In response, at least when the target data is cached in a second cache associated with a second master device, at least one of the coherency control circuitry 10 and the second cache 12 is configured to return a safe-speculative-read response while maintaining the target data in the same coherency state within the second cache. This helps to mitigate against speculative side-channel attacks.