Cache-Coherent Memory Fault Page Handling Without Power Shutdown
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Solution Overview
Problem
Memory devices connected to hosts via cache-coherent interfaces, such as Compute Express Link, face challenges in handling uncorrectable errors in memory cells, leading to unreliable data and lack of effective mechanisms for disabling fault pages during system reboots or reconnections without power shutdown.
Innovation Solution
A device driver uses supplemental commands to retrieve a poison list from the memory device during boot-up, connection, or error detection, converting device physical addresses to host physical addresses, and disabling fault pages to prevent access by applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a memory device is connected to a host through a cache coherent interface, then data access speed and system integration are improved, but uncorrectable errors in memory cells cannot be effectively handled leading to data reliability degradation
Solution Approach 1:
The system performs preliminary scanning of the memory device to identify fault pages before normal operation begins. During device driver probing or system boot-up, the host queries the memory device for fault pages using cache coherent protocol commands, obtaining a poison list of faulty cache lines. This preliminary identification and disabling of fault pages prevents subsequent access to unreliable data, thereby maintaining data reliability while preserving the high-speed cache coherent interface operation.
2Device complexity
If the system uses existing fault handling mechanisms, then implementation complexity is reduced, but fault pages cannot be disabled during system reboots or reconnections without power shutdown
Solution Approach 1:
The fault page handling mechanism is designed to work universally across multiple scenarios including system boot-up, device reconnection, and error detection events. The device driver integrates fault page scanning into existing probing routines and responds to cache coherent protocol commands, making the same mechanism applicable to various system states without requiring separate handling logic for different scenarios.
Solution Approach 2:
The patent introduces a poison list data structure and associated device driver commands as intermediaries between the host and memory device. The poison list stores identified fault pages, and the device driver mediates the scanning, identification, and disabling processes by translating host requests into memory device-specific commands and managing the poison list updates across different operational scenarios.
3Measurement precision
If the host queries the memory device for fault pages using device driver and cache coherent protocol, then fault detection capability is improved, but system operation time during boot-up and connection is increased
Solution Approach 1:
The fault page scanning is performed as a preliminary action during device driver probing or system boot-up sequences, before normal application workloads begin. By integrating the scanning into existing initialization routines rather than adding separate overhead, the system identifies fault pages early without significantly extending overall system operation time.
Solution Approach 2:
The scanning process rushes through the memory device using efficient cache coherent protocol commands to quickly identify fault pages. The device driver implements optimized querying that minimizes the time spent on fault detection by using supplemental commands that can efficiently traverse memory spaces and identify problematic cache lines without exhaustive sequential checking.
Data Source
AI summary
A system and method for fault page handling. In some embodiments, the method includes: querying a memory device for fault pages in the memory device; and receiving a response from the memory device identifying a fault page. The querying of the memory device may include querying the memory device by a device driver; and the querying of the memory device may include querying the memory device using a supplemental command of a cache coherent protocol.