Cache Coherent FPGA Remote Memory Write-Back
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Solution Overview
Problem
Current network architectures for host computer systems make remote memory access less transparent and inefficient due to expensive operations for pages not present locally and made dirty by applications, limiting the utilization of higher network speeds.
Innovation Solution
Employing cache coherent FPGAs to handle remote memory requests by monitoring cache coherence events, identifying dirty cache lines, and periodically copying them back to the remote host, thereby enhancing remote memory write-back operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If remote memory pages are accessed as if local, then memory pool transparency is improved, but write-back operations become expensive and complex
Solution Approach 1:
The patent introduces a cache coherence FPGAs as an intermediary component between the application and remote memory. The FPGA monitors cache coherence events, identifies dirty cache lines, and periodically copies them back to the remote host, thereby mediating the complex write-back operations and making remote memory access transparent to applications
2Reliability
If all dirty pages are written back immediately, then cache coherence is maintained, but network bandwidth is wasted and performance decreases
Solution Approach 1:
Instead of immediately writing back all dirty pages, the system implements periodic write-back operations. The cache coherence FPGA periodically monitors for dirty cache lines and copies them to the remote host at scheduled intervals, reducing unnecessary network traffic while maintaining cache coherence
Solution Approach 2:
The patent extracts only the necessary dirty cache lines from the cache for write-back operations. By monitoring cache coherence events and identifying specifically which cache lines are dirty, the system transfers only the minimal required data to the remote host, avoiding wasteful network bandwidth consumption
3Measurement precision
If cache coherence monitoring is implemented, then dirty cache line identification is improved, but system overhead increases
Solution Approach 1:
The cache coherence FPGA leverages existing cache coherence event streams that are already being generated by the system. Instead of adding separate monitoring mechanisms, the FPGA utilizes these self-generated events to identify dirty cache lines, thereby achieving accurate monitoring with minimal additional overhead
Data Source
AI summary
Disclosed is a method for performing write-back operations to maintain coherence of remote memories in a memory pool. When a local application makes a request for a page of memory that is in the memory pool but not local, a device obtains the page through its RDMA facility and thereafter keeps track of the page for any changes made by the application to the page by storing the page locally and monitoring cache coherency events of cache lines that make up the page. If a requested page become dirty, then periodically the dirty cache lines of the dirty page are written back to the remote memory from which the pages were obtained. In addition, all dirty cache lines are written back when the local memory storing the page becomes full or the application closes a region containing the page.