Cache Coherent Handshake Protocol for Multiprocessor Networks
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Solution Overview
Problem
In multiprocessor systems, cache coherence is compromised due to delays caused by the requirement for acknowledgement messages in cache handshaking protocols, leading to potential data mismatches and reduced processing speed.
Innovation Solution
A cache coherent handshaking protocol that eliminates the need for acknowledgement messages by enforcing a message ordering rule, ensuring that memory requests and responses with the same source node/destination node pair and memory location are transmitted in the same order received, using channel enforcement or cross-posting to maintain coherence without delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If acknowledgement messages are used in cache handshaking protocols, then data integrity is maintained, but processing speed and network throughput are reduced
Solution Approach 1:
The patent extracts and removes the acknowledgement message component from the cache handshaking protocol. By eliminating this component, the protocol reduces message transmission overhead and processing delays while maintaining cache coherence through alternative mechanisms such as order enforcement and snoop-based validation, thereby resolving the contradiction between reliability and speed
Solution Approach 2:
The patent segments the cache coherence maintenance into distinct phases: order enforcement at the network level, snoop-based validation at the cache level, and selective acknowledgement only when necessary. This segmentation allows the system to maintain data integrity through distributed validation rather than sequential acknowledgements, improving overall processing speed while preserving reliability
2Reliability
If acknowledgement messages are required for each cache request, then cache coherence is maintained, but network latency and processor delays increase
Solution Approach 1:
The patent implements preliminary order enforcement at the network element level before messages reach the cache. By pre-ordering messages based on source-destination pairs and memory locations, the system ensures that coherence-critical messages arrive in the correct sequence without requiring time-consuming acknowledgement delays, thus reducing network latency while maintaining cache coherence
Solution Approach 2:
The patent introduces snoop messages as intermediaries that validate cache coherence at the cache level rather than requiring sequential acknowledgements at the network level. These snoop messages enable parallel validation of multiple cache copies, reducing the time penalty associated with maintaining coherence across distributed caches
3Reliability
If message ordering is enforced for all cache transactions, then data mismatches are prevented, but network throughput and scalability are reduced
Solution Approach 1:
The patent applies message ordering enforcement selectively based on local quality requirements: strict ordering is enforced only for message pairs sharing the same source-destination pair and memory location, while other messages can be transmitted without ordering constraints. This localized approach maintains data consistency for critical operations while allowing higher overall network throughput and scalability
Data Source
AI summary
Disclosed herein is a processing network element (NE) comprising at least one receiver configured to receive a plurality of memory request messages from a plurality of memory nodes, wherein each memory request designates a source node, a destination node, and a memory location, and a plurality of response messages to the memory requests from the plurality of memory nodes, wherein each memory request designates a source node, a destination node, and a memory location, at least one transmitter configured to transmit the memory requests and memory responses to the plurality of memory nodes, and a controller coupled to the receiver and the transmitter and configured to enforce ordering such that memory requests and memory responses designating the same memory location and the same source node/destination node pair are transmitted by the transmitter in the same order received by the receiver.