Cache-Coherent Memory Expansion With Pluggable Cache Policies

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Solution Overview

Problem

Existing cache-coherent storage devices suffer from suboptimal performance due to one-size-fits-all policies for data eviction and prefetching, which fail to account for the specific data access patterns of individual applications, leading to increased latency and inefficiency.

Innovation Solution

Incorporation of a pluggable cache policy engine that allows application developers to tailor data eviction and prefetching strategies to the specific needs of their applications, enhancing the cache-coherent storage device's performance by leveraging application-specific data access patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a one-size-fits-all cache policy is used for data eviction and prefetching, then device complexity is reduced and ease of manufacture is improved, but latency increases and access efficiency deteriorates

Engineering Contradiction:
Improvecache policy complexityVSAvoiddata access latency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent implements dynamic cache policies that adapt to different application workloads. The system monitors access patterns and automatically adjusts eviction and prefetching strategies based on the specific application's behavior, transforming static one-size-fits-all policies into dynamic application-aware policies that reduce latency without requiring complex manual configuration

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes cache policy parameters based on application characteristics. By analyzing access patterns and adjusting parameters such as eviction thresholds, prefetch distances, and cache replacement strategies according to each application's specific needs, the system optimizes performance without fundamentally redesigning the cache architecture

Inventive Principle:
Principle #35Parameter changes

2Loss of time

If application-specific cache policies are implemented, then data access latency is reduced and efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvedata access latencyVSAvoidcache policy complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent enables the cache system to automatically analyze application access patterns and self-adjust policies without external intervention. The cache controller monitors workload characteristics and autonomously optimizes eviction and prefetching parameters, reducing the need for complex external configuration while achieving application-specific optimization

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system implements feedback mechanisms where cache performance metrics and access patterns are continuously monitored and fed back to the policy engine. This closed-loop control allows the system to learn from actual usage and automatically refine cache policies, reducing complexity by eliminating manual tuning while maintaining optimization

Inventive Principle:
Principle #23Feedback

3Speed

If DRAM is used to store the entire database, then data access speed is improved, but cost increases

Engineering Contradiction:
Improvedata access speedVSAvoidstorage cost
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent applies local quality by placing frequently accessed data (hot data) in fast DRAM storage while storing less frequently accessed data in slower, cheaper storage media. The system dynamically identifies and prioritizes hot data based on access patterns, ensuring that the most critical data resides in expensive fast storage while reducing overall DRAM requirements and cost

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12541326B2Device cache engine for a cache-coherent interconnect memory expansion
Publication Date: 2026.02.03 SAMSUNG ELECTRONICS CO LTD
  • US12541326B2 patent drawing
  • US12541326B2 patent drawing
  • US12541326B2 patent drawing

AI summary

A memory device is disclosed. The memory device may include an interface to connect the memory device to a processor, a first storage for a data, and a second storage for the data. A controller may process a request received from the processor via the interface using the first storage or the second storage. A policy engine may instruct the controller regarding a storing of the data in the first storage or the second storage.