Cache-Coherent Interconnect Memory for Fast Server Boot
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Solution Overview
Problem
Server reboots in data centers, necessitated by critical firmware updates and disaster recovery, result in significant downtime due to memory retraining, which affects system operations and compute capacity, especially with advanced memory technologies like DDR 5 and increased memory channels.
Innovation Solution
Implementing cache-coherent interconnect memory with pre-allocated regions in a shared memory pool, allowing BIOS to boot the OS from these regions while training local memory in the background, ensuring seamless transition to local memory without interrupting workload execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If server memory is retrained during reboot, then memory reliability is improved, but system downtime increases
Solution Approach 1:
The system performs memory training in advance during previous operations, storing trained memory patterns in a cache-coherent interconnect. When a reboot occurs, the already-trained memory can be quickly restored without repeating the full training sequence, thus maintaining reliability while reducing downtime.
Solution Approach 2:
A cache-coherent interconnect acts as an intermediary between the memory system and the processor. This intermediary maintains cached copies of memory training data, allowing the system to bypass full memory retraining during reboots while ensuring data coherence and reliability is maintained.
2Manufacturing precision
If memory training is performed sequentially, then memory initialization accuracy is improved, but boot speed deteriorates
Solution Approach 1:
The memory training process is segmented into multiple independent training sequences that can execute in parallel. The cache-coherent interconnect divides the memory initialization task across multiple channels or memory banks, allowing simultaneous training operations that maintain accuracy while reducing total boot time.
Solution Approach 2:
Memory training sequences are prepared and validated in advance during system initialization or idle periods. The trained patterns are cached in the cache-coherent interconnect, so during actual boot operations, the system can quickly restore memory state without performing complete training sequences, thereby improving boot speed while maintaining initialization accuracy.
Data Source
AI summary
Systems and methods are provided for implementing server fast boot using cache-coherent interconnect memory. A cache-coherent interconnect node partitions a memory pool and pre-allocates a memory region of the memory pool to each compute node of a plurality of compute nodes. A basic input/output system (“BIOS”) of a compute node maps a local memory of the compute node to a memory region that has been pre-allocated to the compute node. The BIOS boots an operating system (“OS”) of the compute node in the memory region. Concurrent with the OS executing workloads using the memory region, the BIOS trains and initializes the local memory, after completion of which the BIOS notifies the OS that the local memory is ready. The OS migrates contents from the memory region to the local memory, and subsequently executes the workload from the local memory or a combination of the local memory and the memory region.