Cache-Coherent Node Idle-Cycle Probing for Directory Cleanup

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Solution Overview

Problem

Silent evictions in cache-coherent nodes lead to stale coherence directories, causing inefficient evictions, unnecessary messages, performance degradation, and overprovisioning, especially in high-performance computing environments with increasing cores or accelerators, leading to area and power concerns.

Innovation Solution

A coherence directory controller sends periodic probes during network-on-chip idle cycles to check cache presence, allowing the directory to clean itself without core or accelerator intervention, using existing protocols and channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If silent evictions are used to drop clean cache copies without informing coherence directories, then core compute cycles are avoided and message traffic is reduced, but coherence directories become stale leading to inefficient evictions and performance degradation

Engineering Contradiction:
Improvecore compute cyclesVSAvoidcoherence directory accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The coherence directory controller performs preliminary actions by proactively sending probe messages to computing elements before the coherence directory becomes completely stale. This allows the directory to detect and remove entries that may no longer be valid, preventing performance degradation while maintaining the benefits of silent evictions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where the coherence directory controller receives responses from computing elements regarding the presence of cached lines. This feedback loop allows the directory to update its state accurately without requiring computing elements to actively notify the directory of every cache operation, resolving the contradiction between productivity and reliability.

Inventive Principle:
Principle #23Feedback

2Reliability

If coherence directories are overprovisioned to account for stale lines, then directory cleanliness is maintained, but area and power consumption increase

Engineering Contradiction:
Improvedirectory cleanlinessVSAvoidcoherence directory size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The coherence directory controller performs self-service by autonomously sending probe messages and removing stale entries without requiring intervention from computing elements. This self-maintenance capability allows the directory to stay clean with a smaller size, eliminating the need for overprovisioning while maintaining reliability.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system employs periodic actions where the coherence directory controller sends probe messages at scheduled intervals to detect and remove stale entries. This periodic maintenance approach ensures directory cleanliness without requiring continuous monitoring or overprovisioning, thus reducing area and power consumption.

Inventive Principle:
Principle #19Periodic action

3Ease of operation

If coherence directories are not cleaned at cache line eviction time, then silent evictions can proceed without interruption, but all lines appear concurrently used leading to performance degradation

Engineering Contradiction:
Improvesilent eviction operationVSAvoideviction efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The coherence directory controller performs preliminary detection of stale entries by sending probe messages before eviction operations. This allows the system to identify and remove stale lines proactively, ensuring that eviction operations remain efficient and that silent evictions can proceed without interruption to normal computing operations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4506828B1Cache-coherent computer system node and method for cleaning of coherence directories on computer system node to reduce cache-coherence overhead
Publication Date: 2025.09.17 SAMSUNG ELECTRONICS CO LTD
  • EP4506828B1 patent drawingFigure 1
  • EP4506828B1 patent drawingFigure 2

AI summary

A cache-coherent computer system node includes a network-on-chip, a number of computing elements in communication with the network-on-chip, a coherence directory including a number of addresses for cache of the computing elements, a number of coherence states of the addresses, and a number of tracking vectors of the addresses, and a coherence directory controller configured to send a probe to the computing elements during a free cycle of the network-on-chip. The probe is configured to inquire whether an address of the addresses stored in the coherence directory is in the cache of the computing elements, and the coherence directory is configured to clean the coherence directory to remove the address in response to an acknowledgement indicating that the address is not in the cache.