Shared-Memory Cache Consistency via Pseudorandom Message Verification

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Solution Overview

Problem

In multicore processors, ensuring cache consistency between execution cores without reducing system performance or increasing memory storage requirements is challenging, as existing solutions like snooping or time-stamping can lead to inefficiencies and inconsistencies.

Innovation Solution

A method involving pseudorandom binary string generators and cryptographic modules, where both processing units share the same seed and synchronization, enables secure message transmission with integrity checks and headers, ensuring that messages read from shared memory are accurate and up-to-date by using involutive transformations for encryption and decryption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If snooping mechanism is used to ensure cache consistency, then cache consistency is improved, but system performance deteriorates due to slowed cache updating

Engineering Contradiction:
Improvecache consistencyVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent replaces the traditional snooping mechanism (which relies on continuous monitoring and waiting) with a cryptographic verification system using pseudorandom strings and error detection codes. This substitution eliminates the performance penalty of snooping while maintaining consistency through mathematical verification rather than mechanical monitoring.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the fundamental parameter of consistency verification from time-based (waiting for writes to complete) to code-based (using pseudorandom strings and error detection). This parameter change allows cores to verify consistency without temporal delays, resolving the contradiction between consistency and performance.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If time-stamping all write operations is implemented to maintain consistency, then cache consistency is improved, but device complexity increases due to additional data storage requirements

Engineering Contradiction:
Improvecache consistencyVSAvoiddata storage requirements
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the essential consistency verification information into compact cryptographic elements (pseudorandom strings and error detection codes) rather than storing complete time-stamped write operation records. This extraction reduces the storage burden while maintaining verification capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses lightweight, computationally inexpensive verification objects (error detection codes and pseudorandom strings) that can be generated and discarded easily, replacing the need for persistent storage of detailed write operation metadata. These verification objects are 'cheap' in terms of storage and computation.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Reliability

If waiting time is introduced before reading updated data, then cache consistency is improved, but loss of time increases

Engineering Contradiction:
Improvecache consistencyVSAvoidcache updating time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary cryptographic preparation by generating pseudorandom strings and computing error detection codes before actual data writes occur. This preliminary action allows receiving cores to immediately verify consistency without waiting for write completion, eliminating the time loss associated with traditional waiting mechanisms.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9734065B2Method of managing consistency of caches
Publication Date: 2017.08.15 SAFRAN ELECTRONICS & DEFENSE (FR)
  • US9734065B2 patent drawing
  • US9734065B2 patent drawing
  • US9734065B2 patent drawing

AI summary

The present invention relates to a method of transmitting a message comprising an integrity check and a header, between two processing units via a shared memory, comprising steps of: —generation (501), by a first processing unit, of a first pseudorandom binary string; —encryption (502) of the message to be transmitted by applying an involutive transformation dependent on the first pseudorandom binary string generated; —transmission and storage (503) of the encrypted message in the shared memory; —generation (504), by the second processing unit, of a second pseudorandom binary string; —decryption of the message stored by applying an involutive transformation dependent on the second pseudorandom binary string, and by decrypting the header (505) of said message, by verifying the decrypted header (505), and as a function of the result of the verification, by decrypting the complete message (506); —verification (507) of the integrity of the decrypted message on the basis of its integrity check.