Cache Consistency via Virtual Intermediate State S2M
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Solution Overview
Problem
Digital systems with multiple processors sharing a memory face inefficiencies due to complex microprocessor structures and high current consumption caused by frequent cache memory accesses, particularly when transitioning data from a shared state to modified or invalid states using the MESI protocol.
Innovation Solution
The introduction of a virtual intermediate state (S2M) between the shared and modified states in the MESI protocol, where data are temporarily marked as 'memory operation waiting for execution' in the cache and associated memory, reducing the need for multiple cache accesses and optimizing write operations by signaling external operations to all processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the MESI protocol is used to manage cache consistency with modified, shared and invalid states, then cache consistency is maintained, but multiple cache accesses are required which increases current consumption and structural complexity
Solution Approach 1:
The patent introduces an intermediate state S2M between the shared state S and the modified state M. This intermediate state acts as a mediator that reduces the number of cache accesses required during state transitions. When a processor needs to transition from shared to modified state, it first enters the S2M state, which allows the write operation to be performed with fewer cache coherence protocol interactions, thereby reducing current consumption while maintaining consistency.
Solution Approach 2:
The patent segments the state transition process by dividing the direct transition from shared state to modified state into two separate transitions: first to the intermediate S2M state, then to the modified state M. This segmentation allows the system to optimize each transition step independently, reducing the overall number of cache accesses and associated current consumption while preserving cache consistency through controlled state progression.
2Reliability
If multiple cache accesses are performed to transition data from shared state to modified state, then cache consistency is ensured, but the microprocessor structure becomes more complex
Solution Approach 1:
The intermediate S2M state serves as a mediator that simplifies the microprocessor structure by providing a dedicated transition pathway. Instead of requiring multiple complex cache access operations to transition from shared to modified state, the processor simply transitions through the S2M state, which reduces the complexity of the cache coherence logic and state management circuitry while ensuring consistency is maintained throughout the transition.
Solution Approach 2:
By segmenting the state transition into discrete steps (S → S2M → M), the patent reduces microprocessor structure complexity. Each state transition becomes a simple, well-defined operation rather than requiring complex multi-access logic. The intermediate S2M state acts as a buffer that simplifies the control logic needed to manage cache coherence during write operations.
3Reliability
If frequent cache memory accesses are performed for state transitions, then data consistency is maintained, but current consumption increases
Solution Approach 1:
The S2M intermediate state acts as an energy-efficient mediator for state transitions. By introducing this intermediate state, the patent reduces the frequency and number of cache accesses required during transitions from shared to modified state. The intermediate state allows the processor to perform write operations with fewer protocol interactions and cache coherence checks, thereby reducing current consumption while maintaining data consistency through controlled state management.
Solution Approach 2:
The patent segments the energy-consuming cache access operations into distinct state transition steps. By dividing the transition process into S→S2M and S2M→M phases, the system can optimize each phase independently, reducing the total number of cache accesses and associated energy consumption. The intermediate S2M state serves as an energy-efficient staging point that minimizes the frequency of expensive cache coherence operations while preserving data consistency.
Data Source
AI summary
A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state.