Cache Control Data Modification for Access Management

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Solution Overview

Problem

Cache memories in data processing systems consume power and are slow due to the need for frequent flushing and reloading of data, especially during context switches when large amounts of data must be transferred, which is inefficient and power-intensive.

Innovation Solution

Modifying control data within the cache memory using program instructions to manage access permissions, allowing for dynamic changes in access states without the need for cache flushing and reloading, thereby maintaining data validity and reducing power consumption and speed penalties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is flushed from cache memory and reloaded when access control needs to change, then access control is maintained, but processing speed decreases and power consumption increases

Engineering Contradiction:
Improveaccess controlVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the access control information from the data itself and places it in separate control bits associated with the cache lines. This allows the data to remain in cache while the control mechanism is independently managed through bit manipulation, avoiding the need to flush and reload data when access control changes.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements dynamic access control by allowing the control bits to be modified during system operation. The control bits can be changed from indicating one processor has exclusive access to indicating multiple processors can access, enabling adaptive access control without cache flushing.

Inventive Principle:
Principle #15Dynamics

2Reliability

If data is flushed from cache memory and reloaded when access control needs to change, then access control is maintained, but power consumption increases

Engineering Contradiction:
Improveaccess controlVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent extracts the access control information from the data itself and places it in separate control bits associated with the cache lines. This allows the data to remain in cache while the control mechanism is independently managed through bit manipulation, avoiding the need to flush and reload data when access control changes.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent enables continuous data retention in cache by allowing control bits to be modified without evicting the underlying data. This maintains the useful action of data caching while adapting access control, eliminating the interruptive flush-reload cycle that consumes power.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If control data is modified directly in cache memory, then processing speed increases and power consumption decreases, but access control complexity increases

Engineering Contradiction:
Improveprocessing speedVSAvoidaccess control mechanism
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the cache line structure into data portions and control portions. The control bits are separate from the actual data, allowing independent manipulation of access control without affecting the data integrity. This segmentation simplifies the modification process while maintaining control.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The control bits act as an intermediary between the processor and the cached data. Instead of directly manipulating data access permissions through complex control logic, the processor simply modifies these intermediary control bits, which then mediate the access control behavior.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8131942B2Control data modification within a cache memory
Publication Date: 2012.03.06 ARM LTD
  • US8131942B2 patent drawing
  • US8131942B2 patent drawing
  • US8131942B2 patent drawing

AI summary

A data processing system is provided with at least one processor 4, 6, a main memory 18 and a cache memory 14. Cache data within the cache memory 14 has validity data V and control data associated therewith. The control data controls access to the cached data. Program instructions executed by the processors 4, 6 control a cache controller 26 to modify the control data associated with the cached data while it remains stored within the cache memory 14 and remains valid. The control data may, for example, specify a security flags indicating whether access is restricted to secure processes or processors.