Cache Control Device Dynamic Allocation for Real-Time Tasks
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Solution Overview
Problem
Existing cache control methods in parallel processing for real-time control often lead to degraded usability of cache memory due to inefficient allocation of cache areas among tasks, resulting in insufficient allocation to tasks with lower priority and potential failure to complete processing within given real-time limits.
Innovation Solution
A cache control device and method that determine the allocation of cache memory areas based on the allocation ratio of execution time per unit time and processing speed among multiple instruction flows, ensuring balanced resource utilization and adaptive area allocation to maintain high cache hit ratios for all tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache memory area is divided and allocated to multiple tasks based on fixed priority, then interference between tasks is reduced, but usability of overall cache memory is degraded
Solution Approach 1:
The patent applies dynamics by making the cache area allocation ratio changeable according to execution time ratios. The area determination unit dynamically adjusts the cache area allocated to each instruction flow based on its execution time ratio, allowing the system to adapt to varying task priorities and improve overall cache usability while maintaining task execution reliability.
Solution Approach 2:
The patent changes the parameter of cache area allocation from fixed to variable. By determining the allocation ratio based on execution time ratios and allowing this ratio to be changed, the system optimizes cache memory usage while ensuring each task receives appropriate cache resources for reliable execution.
2Speed
If cache area is allocated to tasks with higher priority, then processing speed for high-priority tasks is improved, but cache hit ratio for low-priority tasks deteriorates
Solution Approach 1:
The patent applies local quality by allocating different cache area ratios to different instruction flows based on their specific execution time ratios. Each task receives a cache allocation proportionate to its execution time requirements, ensuring that both high-priority and low-priority tasks maintain appropriate cache hit ratios while preserving processing speed for critical tasks.
Data Source
AI summary
A cache control device includes an area determination unit that determines an area of a cache memory which is allocated to each instruction flow on the basis of an allocation ratio of an execution time per unit time, which is allocated to each of a plurality of the instruction flows by a CPU. The area determination unit specifies the area allocated to the specified instruction flow in response to an access request from a memory access unit, and accesses the specified area in the cache memory.