Cache Control Device with Independent LRU Lists for Read Write Frequency Tracking
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Solution Overview
Problem
In Hierarchical-ARC (H-ARC) systems, the management of data blocks with high update frequency is inefficient due to incorrect classification, leading to degraded cache region efficiency and increased writeback frequency.
Innovation Solution
The implementation of independent LRU lists for managing data blocks based on read frequency (R-series) and write frequency (D-series), where read and write operations are processed separately to maintain accurate frequency tracking without interfering with each other.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If H-ARC manages data blocks in a unified cache region without separate tracking, then the cache management is simpler, but the frequency tracking becomes inaccurate leading to degraded cache efficiency
Solution Approach 1:
The patent divides the unified cache management into separate tracking structures: an R-series LRU list for read frequency tracking and a D-series LRU list for write frequency tracking. This segmentation allows independent management of read and write operations, preventing interference between them while maintaining accurate frequency tracking for both clean and dirty data blocks.
2Device complexity
If H-ARC uses a single LRU list for all data blocks, then the management is more straightforward, but high update frequency data blocks are incorrectly classified leading to increased writeback frequency
Solution Approach 1:
The patent creates separate LRU list structures: R1 and R2 for clean data blocks with different read frequencies, and D1 and D2 for dirty data blocks with different write frequencies. This segmentation ensures that read operations only affect R-series lists and write operations only affect D-series lists, eliminating incorrect classification of high update frequency data blocks.
Solution Approach 2:
The patent introduces intermediate management structures (separate LRU lists) that mediate between read and write operations. These intermediate structures track frequency independently before data blocks are moved between clean and dirty regions, ensuring accurate classification without direct interference between read and write operations.
3Device complexity
If read and write operations share the same LRU list, then the structure is simpler, but frequency tracking interferes with each other reducing cache performance
Solution Approach 1:
The patent segments the LRU list into completely separate structures: R-series lists (R1, R2) for read frequency tracking and D-series lists (D1, D2) for write frequency tracking. This segmentation eliminates interference between read and write operations, as each operation type only affects its designated list structure, thereby maintaining high cache performance.
Data Source
AI summary
A control device includes a cache memory configured to store a first, a second, a third and a fourth list, each of the first, the second, the third and the fourth list storing information indicating data stored in the cache memory, and each of the first, the second, the third and the fourth list being managed under a LRU algorithm, and when first data stored in the storage device is accessed, register first information indicating the first data into the first list, and when the first data is stored in the storage device, register second information indicating the first data into the second list, a processor coupled to the memory and configured to receive a first request for reading the first data, and based on the first request, move the first information from the first list to the third list, while remain the second information in the second list.