Cache Controller Modes for Adaptive Memory Access
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Solution Overview
Problem
Existing memory systems with multi-level cache hierarchies face inefficiencies in cache allocation and transaction processing, particularly in handling cache coherence states and prioritization of transactions in the pipeline, leading to potential stalls and reduced performance.
Innovation Solution
Implementing dynamic transaction arbitration and cache allocation strategies, including random selection of cache ways, prioritization of transactions based on priority levels, and switching between caching and non-caching modes, along with aliased memory operations, to optimize cache utilization and transaction handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache allocation follows strict coherence state checking, then cache consistency is maintained, but allocation speed and throughput are reduced
Solution Approach 1:
The patent implements dynamic cache allocation by allowing the cache controller to adaptively select between strict coherence checking and relaxed allocation based on current system state. The controller dynamically adjusts allocation policies depending on whether ways are valid or invalid, and whether pending requests exist, thereby maintaining consistency when necessary while improving throughput when possible.
Solution Approach 2:
The system changes the parameter of allocation strictness based on cache way validity states. When ways are invalid, the system relaxes coherence checking parameters to allow faster allocation. When ways are valid, stricter parameters are applied to maintain consistency. This parameter adaptation resolves the contradiction between reliability and productivity.
2Productivity
If random way selection is used when no invalid ways are available, then cache utilization is improved, but risk of conflict with pending requests increases
Solution Approach 1:
The patent performs preliminary checking of pending requests before finalizing random way selection. The cache controller checks whether selected ways have pending requests and, if so, selects alternative ways. This preliminary action prevents conflicts while maintaining the benefits of random selection for improving cache utilization.
Solution Approach 2:
The system introduces an intermediary checking mechanism between random selection and final allocation. The controller acts as an intermediary that validates random selections against pending request states and adjusts selections accordingly, thereby mediating between the goals of high utilization and low conflict.
3Speed
If priority-based transaction processing is implemented, then critical transactions are handled faster, but system complexity increases
Solution Approach 1:
The patent segments transactions into different priority levels (high priority and low priority). The arbitration logic is segmented to handle high priority transactions separately from low priority ones. This segmentation allows critical transactions to be processed faster while keeping the arbitration logic relatively simple through modular design.
Data Source
AI summary
An apparatus includes a CPU core, a first cache subsystem coupled to the CPU core, and a second memory coupled to the cache subsystem. The first cache subsystem includes a configuration register, a first memory, and a controller. The controller is configured to: receive a request directed to an address in the second memory and, in response to the configuration register having a first value, operate in a non-caching mode. In the non-caching mode, the controller is configured to provide the request to the second memory without caching data returned by the request in the first memory. In response to the configuration register having a second value, the controller is configured to operate in a caching mode. In the caching mode the controller is configured to provide the request to the second memory and cache data returned by the request in the first memory.