Cache Controller for Multi-Source Code Fetch and Authentication
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Solution Overview
Problem
Existing methods for updating cached software code face challenges in efficiently and securely fetching code from external Non-Volatile Memory (NVM) due to long access latencies, which degrade runtime performance and security, especially when using asymmetric authentication schemes are slow and symmetric schemes are insufficiently strong.
Innovation Solution
A cache controller manages a pool of hosts and an NVM, prioritizing code fetching from available hosts over NVM, using a hierarchical authentication scheme with asymmetric and symmetric cryptographic methods to ensure security and efficiency, and dynamically reallocating hosts based on operability and workload.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of stationary object
If code is fetched from external NVM, then code storage capacity is increased, but access latency increases and runtime performance degrades
Solution Approach 1:
The code storage is segmented into multiple sources: local cache memory for frequently accessed code, external NVM for bulk storage, and multiple host systems for redundancy. The cache controller divides code fetching operations into segments, attempting to serve from faster local cache first, then escalating to external NVM or hosts only when necessary, thereby reducing average access latency while maintaining increased storage capacity
Solution Approach 2:
The system performs preliminary actions by pre-loading and caching code segments into local cache memory before they are actually needed for execution. The cache controller proactively manages cache contents, anticipating code access patterns and pre-fetching segments, which reduces the latency of actual code execution by having code ready in faster memory before it is needed
2Reliability
If asymmetric authentication schemes are used for code verification, then security is strengthened, but authentication speed decreases and runtime performance degrades
Solution Approach 1:
The authentication process is segmented into two distinct phases: an initial asymmetric authentication phase that establishes security credentials and generates authentication tokens, followed by a symmetric authentication phase that uses these tokens for rapid verification of subsequent code segments. This segmentation allows the system to enjoy the security benefits of asymmetric schemes while achieving the speed of symmetric schemes during runtime
Solution Approach 2:
The system performs preliminary asymmetric authentication to establish security credentials and generate authentication tokens before code execution begins. These pre-established credentials are then reused for subsequent code verification, eliminating the need to perform slow asymmetric cryptography during runtime and thereby maintaining both high security and fast authentication speed
3Reliability
If multiple hosts are allocated for code fetching, then system availability is improved, but device complexity and arbitration overhead increase
Solution Approach 1:
The host allocation is made dynamic rather than static. The cache controller continuously monitors the operational status of allocated hosts and dynamically adjusts allocations in real-time. When a host becomes unavailable, the system dynamically reassigns its workload to other available hosts, and when hosts become available, they are dynamically added to the allocation pool. This dynamic approach improves availability while managing complexity through adaptive rather than rigid host management
Solution Approach 2:
The cache controller serves as an intermediary between the processor and multiple host systems. It abstracts the complexity of multi-host management by providing a unified interface for code fetching, handling host status monitoring, selection, and failover logic internally. This intermediary role shields the processor from host management complexity while maintaining high availability through coordinated multi-host operations
Data Source
AI summary
A peripheral device includes a processor, a memory interface, a host interface and a cache controller. The processor executes software code. The cache memory caches a portion of the software code. The memory interface communicates with a NVM storing a replica of the software code. The host interface communicates with hosts storing additional replicas of the software code. The cache controller is to determine whether each host is allocated for code fetching, to receive a request from the processor for a segment of the software code, when available in the cache memory to fetch the segment from the cache memory, when unavailable in the cache memory and at least one host is allocated, to fetch the segment from the hosts that are allocated, when unavailable in the cache memory and no host is allocated, to fetch the segment from the NVM, and to serve the fetched segment to the processor.