Cache Controller Redundancy for Data Recovery
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Solution Overview
Problem
Current data storage systems, particularly hard disk drives, have not scaled effectively to keep pace with the rapid growth in data generation, leading to performance bottlenecks in accessing and storing large volumes of data, even with advancements in data transmission rates.
Innovation Solution
A networked storage system utilizing redundant components and Flash solid state drive circuits with cache management services, including Flash-backed DRAM and cache controllers, to enhance data access and storage performance by providing high-speed connections and redundancy, ensuring data integrity and availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If hard disk drives are used for data storage, then large volumes of data can be accommodated, but data access rates remain slow and do not scale with data volume
Solution Approach 1:
The storage system is segmented into two distinct components: Flash storage circuits for high-speed data access and hard disk drives for large-volume storage. The Flash circuits handle frequently accessed data requiring high speed, while HDDs store bulk data, allowing each component to operate in its optimal performance range without compromising overall system speed or capacity.
Solution Approach 2:
Flash storage circuits act as an intermediary layer between the host system and hard disk drives. This intermediary provides high-speed buffer storage that mediates the speed mismatch between fast host processors and slow HDD access rates, enabling the system to handle large volumes of data at high speeds by caching frequently accessed data in Flash memory.
2Productivity
If transmission data rates are increased to handle growing data volumes, then throughput in communication channels is enhanced, but storage subsystem performance becomes the limiting bottleneck
Solution Approach 1:
The storage subsystem is segmented into Flash storage circuits for high-speed operations and hard disk drives for bulk storage. This segmentation allows the Flash component to handle high-throughput data transmission tasks requiring fast access, while HDDs provide reliable bulk storage, preventing the storage subsystem from becoming a bottleneck in high-speed data transmission environments.
3Speed
If Flash storage is used to improve data access speed, then high-speed data access is achieved, but the lifespan of Flash storage is reduced due to increased write operations
Solution Approach 1:
Data is copied between Flash storage circuits and hard disk drives based on access patterns. Frequently accessed data is cached in Flash memory for high-speed access, while less frequently accessed data is stored on HDDs. This copying strategy minimizes write operations to Flash storage by only caching data that requires fast access, thereby extending Flash storage lifespan while maintaining high-speed access performance for critical data.
Solution Approach 2:
The system dynamically discards data from Flash storage to hard disk drives when access frequency decreases or Flash capacity is needed, and recovers data back to Flash when access patterns indicate high frequency requirements. This dynamic data movement optimizes Flash storage utilization and extends its operational lifespan by reducing unnecessary write cycles while maintaining high-speed access capability.
Data Source
AI summary
A system comprises a first host device, a second host device, and first and second cache controllers. A cache controller includes a cache memory interface, a first peripheral interface that communicates with the first host device, a second peripheral interface that communicates with the second host device, logic circuitry that loads a cache command from a cache command memory of the first host device, loads a cache command from a cache command memory of the second cache controller, and performs the cache commands, and error checking circuitry that detects an uncorrectable error in a first cache controller/memory pair and indicates the uncorrectable error condition to at least one of the first and second host devices. At least one of the first host device or the second host device writes contents of the cache memory of the second cache controller/memory pair to a main memory in response to the indication.