Cache Controller Delaying Invalidation Messages for Bandwidth Reduction
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Solution Overview
Problem
In complex multiprocessor systems, cache coherence invalidation messages place severe demands on bandwidth, energy consumption, and heat generation, as they must be transmitted promptly to maintain data consistency across multiple processors accessing a shared main memory.
Innovation Solution
A cache controller delays and combines multiple invalidation messages related to a common region of memory during data-race free program execution, reducing the need for immediate transmission and optimizing communication by using a single combined message, which includes bit vectors and address offsets to eliminate redundant information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If invalidation messages are transmitted immediately to preserve cache coherence, then data consistency is maintained, but network bandwidth consumption increases severely
Solution Approach 1:
The patent combines multiple individual invalidation messages into a single batched invalidation message. Instead of sending separate invalidation messages for each cache line modification, the system accumulates multiple invalidation requests and transmits them together in one message, significantly reducing the total number of messages sent across the interconnect network while maintaining cache coherence.
Solution Approach 2:
The system performs preliminary accumulation of invalidation messages before transmission. By buffering and collecting multiple invalidation requests over time before sending them out as a batch, the system prepares the invalidation data in advance, reducing immediate network traffic while ensuring coherence is eventually maintained.
2Reliability
If multiple individual invalidation messages are sent for each cache line modification, then cache coherence is maintained, but energy consumption increases significantly
Solution Approach 1:
The patent merges multiple individual invalidation message transmissions into a single combined transmission event. By batching multiple invalidation requests and sending them together in one message, the system reduces the total number of transmission operations required, thereby significantly reducing the cumulative energy consumption associated with message transmission across the interconnect.
3Reliability
If invalidation messages are sent immediately for each cache modification, then data consistency is maintained, but heat generation increases
Solution Approach 1:
The patent combines multiple invalidation message transmissions into a single batched transmission. By accumulating multiple invalidation requests and sending them together in one message rather than transmitting each individually, the system reduces the frequency of transmission operations, thereby reducing the cumulative heat generated by the interconnect and communication infrastructure.
4Quantity of substance
If invalidation messages are delayed for batching, then network traffic is reduced, but transmission timing becomes more complex
Solution Approach 1:
The system implements preliminary buffering of invalidation messages with associated timing and validity metadata. By pre-processing and storing invalidation requests with their timing information before batch transmission, the system manages the complexity of delayed transmission through structured preliminary organization of the data, enabling efficient batch processing while maintaining coherence requirements.
Data Source
AI summary
A computer cache system delays cache coherence invalidation messages related to cache lines of a common memory region to collect these messages into a combined message that can be transmitted more efficiently. This delay may be coordinated with a detection of whether the processor is executing a data-race free portion of the program so that the delay system may be used for a variety of types of programs which may have data-race and data-race free sections.