Cache Controller Miss Queue Merging for Non-Coherent Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current computing systems face performance issues due to the inability to efficiently merge non-cacheable load miss requests targeting the same address range, leading to increased memory access latency and reduced system performance.
Innovation Solution
A cache controller with a miss queue that merges non-cacheable load miss requests targeting the same address range into a single merged miss request, utilizing timers and size thresholds to manage the merging process while maintaining memory ordering consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-cacheable load miss requests are not merged, then memory ordering consistency is preserved, but system performance deteriorates due to repeated memory accesses
Solution Approach 1:
The patent merges multiple non-cacheable load miss requests targeting the same address range into a single merged miss request. The merge queue stores incoming miss requests and combines them when they target overlapping address ranges, reducing the number of separate memory access operations while maintaining the original ordering through timestamp tracking.
2Loss of time
If non-cacheable load miss requests are merged, then memory access latency is reduced, but device complexity increases due to merge queue management
Solution Approach 1:
The patent segments the miss request handling process into distinct stages: receiving requests in a merge queue, determining address range overlaps, merging compatible requests, and issuing merged requests to the lower cache level. This segmentation manages complexity by organizing the merging logic into modular, manageable components.
Solution Approach 2:
The merge queue acts as an intermediary between the load/store unit and the lower cache level. It buffers miss requests, performs merging operations, and manages the complexity of request consolidation while maintaining the simple interface for both the processor and the memory hierarchy.
3Productivity
If multiple miss requests are merged into a single cache fill, then the number of memory accesses is reduced, but the quantity of data transferred increases
Solution Approach 1:
The patent applies partial action by merging only those miss requests that target overlapping address ranges, rather than merging all requests indiscriminately. The system selectively combines requests based on address range analysis, merging enough requests to improve performance while avoiding unnecessary data transfer for requests with different address targets.
Data Source
AI summary
A system and method for efficiently forwarding cache misses to another level of the cache hierarchy. Logic in a cache controller receives a first non-cacheable load miss request and stores it in a miss queue. When the logic determines the target address of the first load miss request is within a target address range of an older pending second load miss request stored in the miss queue with an open merge window, the logic merges the two requests into a single merged miss request. Additional requests may be similarly merged. The logic issues the merged miss requests based on determining the merge window has closed. The logic further prevents any other load miss requests, which were not previously merged in the merged miss request before it was issued, from obtaining a copy of data from the returned fill data. Such prevention in a non-coherent memory computing system supports memory ordering.