Cache Controller Partial Aggregation for Memory Access Reduction

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Solution Overview

Problem

Computing apparatuses with limited resources, such as communication bandwidth and energy consumption, face challenges in increasing processing performance due to frequent memory access, which reduces energy efficiency and processing time.

Innovation Solution

A computing apparatus configuration that includes a core device, cache memory, and cache controller to perform partial operations on aggregation operands, reducing the need for frequent memory access by storing and processing results within the cache memory, thereby improving energy efficiency and processing speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the processor frequently accesses memory to process aggregation operations, then processing completeness is improved, but energy consumption increases and processing speed decreases

Engineering Contradiction:

Improveprocessing speedVSAvoidenergy consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent segments the aggregation operation into two distinct phases: a first partial operation executed by the cache controller using operands from cache memory, and a second partial operation executed by the processor using the cached result and a variable from main memory. This segmentation allows the energy-intensive memory access to occur only once per aggregation operation rather than multiple times, thereby reducing overall energy consumption while maintaining processing completeness.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The cache controller performs the first partial operation in advance, computing an intermediate result and storing it in cache memory before the processor needs to access main memory. This preliminary action eliminates the need for the processor to repeatedly access main memory during the aggregation operation, reducing both energy consumption and access time while preserving the ability to complete the full aggregation.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If the processor frequently accesses memory to process aggregation operations, then processing completeness is improved, but processing time increases

Engineering Contradiction:

Improveprocessing speedVSAvoidprocessing time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The aggregation operation is divided into two segments: the first partial operation handled by the cache controller using cached operands, and the second partial operation handled by the processor using the cached intermediate result and one variable from main memory. This segmentation reduces the number of main memory access operations, thereby decreasing total processing time while ensuring the aggregation is completed correctly.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The cache controller performs the first partial operation before the processor accesses main memory, storing the intermediate result in cache memory. This preliminary computation reduces the processing time by eliminating repeated main memory accesses during the aggregation operation, as the processor only needs to retrieve one variable and one cached result rather than multiple operands from slow main memory.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If aggregation operations are performed using operands from main memory, then operational accuracy is improved, but communication bandwidth consumption increases

Engineering Contradiction:

Improveoperational accuracyVSAvoidcommunication bandwidth consumption

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent segments the data access pattern so that aggregation operands are retrieved from cache memory for the first partial operation, and only one variable is retrieved from main memory for the second partial operation. This segmentation reduces the volume of data transmitted over the processor-memory interface, decreasing communication bandwidth consumption while maintaining operational accuracy through the use of precise arithmetic operations in both phases.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The cache controller performs preliminary processing of aggregation operands stored in cache memory, computing intermediate results before the processor needs to access main memory. This approach reduces the amount of data that must be communicated between main memory and the processor, as only the final variable and intermediate cache results are exchanged, thereby reducing bandwidth consumption while preserving computational accuracy.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10990589B2Computing apparatuses and methods of processing operations thereof

Publication Date: 2021.04.27 SAMSUNG ELECTRONICS CO LTD

AI summary

A computing apparatus may process an operation. The computing apparatus may output information regarding an aggregation operation and an operand corresponding to a variable stored in a memory, store information regarding an operator and the aggregation operands regarding the aggregation operation, perform a first partial operation with respect to the aggregation operands and store a result value of the first partial operation, and process the aggregation operation based on storing the variable, performing a second partial operation with respect to the result value of the first partial operation stored in the cache and the operand corresponding to the variable, and storing a result value of the second partial operation.