Cache Memory Controller Partial Tag Comparison
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Solution Overview
Problem
Modern semiconductor manufacturing faces challenges with increasing interconnect delays and high electrical impedance in two-dimensional planar layout chips, leading to significant memory access latencies and power consumption issues due to parasitic capacitance, particularly in accessing off-chip DRAM.
Innovation Solution
A random access memory cache memory controller is introduced that divides memory access requests into tag and data access requests, performing a partial tag comparison to determine cache hits within a last-level cache (LLC) before sending data access requests, thereby reducing latency and power consumption by optimizing memory access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If memory access requests are sent to off-chip DRAM, then data can be retrieved, but memory access latency increases significantly (hundreds to over a thousand clock cycles)
Solution Approach 1:
The patent segments memory access requests into two separate requests: a tag access request sent to system memory to check cache validity, and a data access request sent to the memory device. This segmentation allows the system to determine cache hits before initiating full data transfers, thereby reducing overall memory access latency and improving computational throughput.
2Loss of energy
If signals traverse off-chip to another die, then data can be transferred, but power consumption increases significantly (10 to 100 times) due to increased parasitic capacitance
Solution Approach 1:
The patent performs a preliminary tag comparison in the cache memory controller before initiating data access requests to off-chip DRAM. By checking cache validity tags first, the system可以避免 unnecessary off-chip data transfers, thereby reducing power consumption associated with parasitic capacitance while maintaining data transfer capability when needed.
3Productivity
If the cache memory controller sends data access requests without checking cache hits first, then data access can proceed, but memory bandwidth is wasted on cache misses
Solution Approach 1:
The patent implements a preliminary tag comparison step where the cache memory controller checks cache hits by comparing tags before sending data access requests to the memory device. This preliminary action ensures that data access requests are only sent when cache hits are confirmed, optimizing memory bandwidth utilization and reducing access latency.
4Measurement precision
If full tag comparison is performed for every memory access request, then cache accuracy is maintained, but access time increases
Solution Approach 1:
The patent employs partial tag comparison instead of full tag comparison for cache hit detection. The cache memory controller compares only a portion of the tag (e.g., upper bits) to determine cache hits, which reduces comparison time while maintaining sufficient accuracy for the application.
Data Source
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AI summary
Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. External system memory is used as a last-level cache and includes one of a variety of types of dynamic random access memory (DRAM). A memory controller generates a tag request and a separate data request based on a same, single received memory request. The sending of the tag request is prioritized over sending the data request. A partial tag comparison is performed during processing of the tag request. If a tag miss is detected for the partial tag comparison, then the data request is cancelled, and the memory request is sent to main memory. If one or more tag hits are detected for the partial tag comparison, then processing of the data request is dependent upon the result of the full tag comparison.