Cache Controller Prefetching for Semiconductor Devices
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Solution Overview
Problem
In semiconductor devices with multi-way cache memory, there is a risk of cache misses occurring frequently during continuous access operations, especially when one way has limited memory capacity, leading to inefficiencies in cryptographic operations and increased power consumption.
Innovation Solution
A semiconductor device with a cache controller that autonomously switches between treating multiple ways as independent or combined for prefetching, based on access history, by adjusting the address change direction flag and tag values to optimize data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If prefetching is performed in a multi-way cache memory, then data access efficiency is improved, but cache miss rate increases when memory capacity is limited
Solution Approach 1:
The cache controller dynamically switches between two operational modes: a multi-way cache mode for normal operations and a single-way prefetch mode when continuous access patterns are detected. This dynamic adaptation allows the system to optimize for either parallel storage or sequential prefetching based on actual access patterns, resolving the contradiction between improving data access efficiency and maintaining low cache miss rates with limited memory capacity.
Solution Approach 2:
The system changes the operational parameters of the cache memory by switching the number of active ways between one and multiple based on detected access patterns. When continuous access is detected, the system transitions to using a single way for prefetching operations, thereby preventing cache misses while maintaining efficient data access during normal multi-way operations.
2Quantity of substance
If multiple ways are used for continuous access, then data storage capacity is improved, but power consumption increases
Solution Approach 1:
The cache controller dynamically adjusts the number of active cache ways based on access patterns. During continuous access operations, only one way is activated for prefetching, significantly reducing power consumption compared to keeping multiple ways active. During normal operations, multiple ways are utilized to maintain data storage capacity and access efficiency.
3Speed
If prefetching is performed without dynamic mode switching, then data access speed is improved, but cache memory efficiency deteriorates
Solution Approach 1:
The system changes the operational mode parameter of the cache memory based on detected access patterns. When continuous access is detected, the system switches to a single-way prefetch mode that optimizes for access speed. During normal operations with varied access patterns, the system operates in multi-way mode to maximize cache memory efficiency and utilization.
Data Source
AI summary
A semiconductor device includes a processor, a memory, a plurality of tags, a plurality of ways each of which can store a plurality of data of consecutive addresses of the memory in which a tag value stored in each tag of the plurality of tags is taken as a reference address, and a cache controller configured to determine whether a second way has an address change direction flag matching an address change direction flag of the first way and has a tag value continuous with a tag value of the first way in a direction opposite to a direction that the address change direction flag of the first way indicates and prefetch data indicated by a tag value continuous with the tag value of the first way in the direction that the address change direction flag indicates to the second way based on the result of the determination.