Configurable Cache Controller Serial Lookup Power Optimization

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Solution Overview

Problem

Multi-core processing systems face challenges in efficiently managing cache memory access to balance performance and power consumption, particularly in reducing access/snoop bandwidth while conserving dynamic power.

Innovation Solution

An N-way set associative cache memory system with a configurable cache controller that performs cache lookups in parallel using N ways or serially using subsets of M ways, where M<N, to optimize access and reduce power consumption based on the system's power state and type of access requests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If cache lookups are performed on all N tag ways concurrently, then access bandwidth and latency are improved, but power consumption increases

Engineering Contradiction:
Improveaccess bandwidthVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The cache controller dynamically adjusts the lookup strategy between parallel and serial modes based on system state, enabling adaptive optimization of the trade-off between access speed and power consumption

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the operational parameters of the cache controller by adjusting the degree of parallelism (from N-way parallel to serial) based on power state and access type, thereby optimizing performance under different conditions

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If cache lookups are performed serially on subsets of M tag ways, then power consumption is reduced, but access bandwidth and latency worsen

Engineering Contradiction:
Improvepower consumptionVSAvoidaccess bandwidth
Core Design Contradiction:
Use of energy by moving objectVSSpeed

Solution Approach 1:

The cache controller dynamically switches between serial and parallel lookup modes depending on power state and access type, allowing the system to reduce power consumption when high performance is not critical

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system performs partial parallel lookups by processing subsets of M tag ways concurrently rather than all N ways, achieving a balance between power savings and acceptable access performance

Inventive Principle:
Principle #16Partial or excessive action

3Adaptability or versatility

If the cache controller is configured to dynamically adjust lookup method, then adaptability is improved, but device complexity increases

Engineering Contradiction:
Improveoperational flexibilityVSAvoidcontroller complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The cache controller implements dynamic reconfiguration capability to switch between parallel and serial lookup modes based on system state, enhancing adaptability while managing complexity through state-based control logic

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10324850B2Serial lookup of tag ways
Publication Date: 2019.06.18 MICROSOFT TECHNOLOGY LICENSING LLC
  • US10324850B2 patent drawing
  • US10324850B2 patent drawing
  • US10324850B2 patent drawing

AI summary

A cache system is configurable to trade power consumption for cache access latency. When it is desired for a system with a cache to conserve dynamic power, the lookup of accesses (e.g., snoops) to cache tag ways is serialized to perform one (or less than all) tag way access per clock (or even slower). Thus, for an N-way set associative cache, instead of performing a lookup/comparison on the N tag ways in parallel, the lookups are performed one tag way at a time. This take N times more cycles thereby reducing the access/snoop bandwidth by a factor of N. However, the power consumption of the serialized access when compared to ‘all parallel’ accesses/snoops is reduced.