Cache Controller Stack Area Useless Information Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Caches in electronic devices perform unnecessary operations on data that has been discarded, such as writing back popped data to main memory, leading to inefficiency and security issues due to lack of recognition of data redundancy.
Innovation Solution
A cache system with a data memory, tag memory, and cache controller that manages data in a stack structure, where the cache controller changes the useless information of a cache line to a useless state upon a pop request, preventing unnecessary operations and enhancing security by outputting dummy data for read requests on popped data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the cache stores popped data without deletion, then data availability is maintained, but unnecessary operations are performed and security problems occur
Solution Approach 1:
The patent extracts the harmful aspect of stored popped data by introducing a separate tag memory that stores only metadata (validity and population status) about cache lines, separating the actual data storage from the management information. This allows the cache to maintain data availability while enabling precise identification and handling of popped data through tag entries.
Solution Approach 2:
The tag memory acts as an intermediary between the data memory and the controller, providing intermediate information about cache line status. The tag entries serve as mediators that convey validity and population state without storing the actual data, allowing the controller to make informed decisions about whether to perform write-back operations or respond to read requests.
2Reliability
If the cache performs write-back operations on all cache lines, then data consistency is maintained, but processing time increases due to unnecessary operations
Solution Approach 1:
Instead of performing write-back operations on all cache lines (excessive action), the patent applies partial action by using tag memory to identify only those cache lines that actually contain valid, non-popped data requiring write-back. The population bit in tag entries enables selective operation only on necessary cache lines, reducing processing time while maintaining data consistency.
Solution Approach 2:
The tag memory performs preliminary classification of cache lines into valid, invalid, and populated states before write-back operations are needed. This preliminary action of tagging and categorizing cache lines allows the controller to pre-determine which lines require write-back, avoiding unnecessary operations and reducing processing time.
3Ease of operation
If the cache stores popped data for future read requests, then data accessibility is improved, but security vulnerabilities are introduced
Solution Approach 1:
The tag memory provides feedback to the controller about the population status of each cache line. When a read request arrives, the controller checks the population bit in the tag entry to determine whether the data was recently popped. This feedback mechanism enables the controller to distinguish between legitimately accessible data and security-sensitive popped data, allowing selective response to read requests.
Data Source
AI summary
A cache includes a data memory, a tag memory, and a cache controller. The data memory includes a stack area storing, in a stack structure, data used by an external processor in a plurality of cache lines. The tag memory stores a tag entry including useless information indicating whether data stored in a corresponding cache line has been popped. The cache controller is configured to, when a pop request for data stored in the stack area is received, change the useless information of a cache line storing the data subject to the pop request, to a useless state.