Cache Memory Controller Merging Store Requests

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Solution Overview

Problem

Current cache memory systems face inefficiencies in handling cache updates, particularly when multiple store requests are directed to the same cache line, leading to increased power consumption and latency.

Innovation Solution

Implementing a method where the cache memory controller receives multiple store requests and concurrently stores the associated data units to a given cache line in a single cache update operation, if determined that all data units are designated for storage in that cache line.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple store requests are handled separately in cache memory, then each request is processed individually ensuring data accuracy, but the number of cache update operations increases leading to higher power consumption and latency

Engineering Contradiction:
Improvedata accuracyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent combines multiple store requests into a single cache update operation when they target the same cache line. The cache memory controller identifies multiple store requests designated for the same cache line and merges them into one atomic update operation, reducing the total number of cache update operations while maintaining data accuracy through proper handling of store request ordering and validation.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If multiple store requests are handled separately in cache memory, then each request is processed individually ensuring proper ordering, but the latency increases due to multiple sequential update operations

Engineering Contradiction:
Improverequest orderingVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent merges multiple store requests into a single cache update operation to reduce latency. By combining requests that target the same cache line into one atomic operation, the system reduces the sequential processing time while maintaining proper request ordering through validation logic that ensures correctly ordered processing of merged requests.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If multiple store requests are handled separately in cache memory, then data consistency is maintained through individual updates, but the number of cache update operations increases reducing system efficiency

Engineering Contradiction:
Improvedata consistencyVSAvoidsystem efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges multiple store requests into a single cache update operation to improve system efficiency. By reducing the number of cache update operations through intelligent merging of requests targeting the same cache line, the system achieves better throughput and productivity while maintaining data consistency through proper validation and ordering mechanisms.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250130945A1System and method for handling cache updates
Publication Date: 2025.04.24 AMPERE COMPUTING LLC
  • US20250130945A1 patent drawing
  • US20250130945A1 patent drawing
  • US20250130945A1 patent drawing

AI summary

A method of controlling a cache memory is disclosed. In an aspect, the method comprises receiving two or more store requests, wherein each store request is associated with a respective data unit for storage in the cache memory; and concurrently storing the respective data units associated with the two or more store requests to a given cache line of the cache memory in a single cache update operation based on determining that the respective data units associated with the two or more store requests are designated for storage in the given cache line.