Cache Controller Traffic Class Allocation
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Solution Overview
Problem
Current computing systems face challenges in prioritizing and managing high-priority data transactions in cache memory, as technologies like Data Direct I/O (DDIO) are ineffective due to the inability to differentiate and allocate cache access based on traffic classes, leading to cache misses and reduced performance in real-time applications.
Innovation Solution
The implementation of PCIe traffic class bits to selectively store data in cache memory or system memory based on traffic class, allowing for traffic class-level resolution in cache allocation, ensuring high-priority data is maintained in cache while evicting lower-priority data when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If Data Direct I/O is used to allow IO transactions to target Cache directly, then cache access speed is improved, but high priority transactions cannot be differentiated from low priority transactions leading to ineffective prioritization
Solution Approach 1:
The patent applies local quality by differentiating cache allocation behavior based on traffic class. High priority transactions receive preferential cache allocation while low priority transactions use remaining cache resources. This is implemented through separate cache way masks for different traffic classes, allowing each traffic class to have its own cache allocation policy rather than a uniform approach.
Solution Approach 2:
The patent changes the parameter of cache allocation by introducing traffic class as a differentiating factor. The cache controller modifies cache way mask allocation based on traffic class priority, dynamically adjusting which cache ways are available to each traffic class. This parameter change enables prioritization without requiring separate physical caches.
2Productivity
If cache memory is shared among all IO transactions, then cache utilization is maximized, but high priority real-time data cannot be guaranteed to remain in cache during evictions
Solution Approach 1:
The patent segments the cache allocation mechanism by introducing separate cache way masks for different traffic classes. This segmentation allows the cache controller to manage cache resources differently for high priority and low priority transactions, ensuring that high priority data can be protected from eviction by allocating specific cache ways exclusively to high priority traffic.
Solution Approach 2:
The patent implements preliminary action by pre-configuring cache way masks for different traffic classes before actual data transmission occurs. The cache controller is programmed with allocation policies that determine cache way assignment in advance, allowing it to immediately enforce prioritization when transactions arrive without needing to make dynamic decisions during cache pressure situations.
3Adaptability or versatility
If traffic class-level resolution is implemented in cache allocation, then high priority data prioritization is achieved, but cache controller complexity increases
Solution Approach 1:
The patent achieves universality by making the existing cache way mask mechanism serve multiple functions. The same cache way mask infrastructure that controls basic cache allocation is extended to also handle traffic class prioritization. This allows the cache controller to maintain existing cache management functionality while adding prioritization capabilities without requiring entirely separate control logic.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of traffic class identifiers that are extracted from incoming transactions and used to index into pre-configured cache way mask tables. This intermediary approach simplifies the cache controller logic by using a lookup-based system rather than complex real-time arbitration, reducing the computational burden on the cache controller while still achieving fine-grained prioritization.
Data Source
AI summary
This disclosure pertains to using traffic classes to selectively store data into cache memory or into system memory. A cache controller can map the traffic class of incoming data to portions of the cache memory allocated for corresponding traffic classes of data.