Cache Copy Logic Reduces System Bus Traffic
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Solution Overview
Problem
Existing data copying techniques, such as PIO and DMA, lead to heavy CPU load and system bus bandwidth occupancy, resulting in decreased system performance due to excessive bus traffic.
Innovation Solution
A cache system with copy logic, connected to both the processor via a system bus and the memory controller via a local bus, performs data copying independently, reducing bus traffic by buffering data and allowing the memory controller to read and write data directly to a memory block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PIO technique is used for data copying, then data copying can be performed, but heavy load occurs on the CPU and system becomes slow
Solution Approach 1:
The patent extracts the data copying function from the CPU by introducing a dedicated copy logic unit within the cache. This separate copying mechanism handles data transfer independently, removing the burden from the CPU and preventing it from becoming a bottleneck in the copying process.
Solution Approach 2:
The cache with integrated copy logic acts as an intermediary between the CPU and memory. It receives copy commands from the CPU through the system bus and executes the copying operation using its own dedicated logic and buffer, mediating the data transfer without requiring continuous CPU intervention.
2Device complexity
If DMA technique is used for data copying, then CPU load is reduced, but the CPU unnecessarily occupies the bandwidth of the system bus
Solution Approach 1:
The cache serves as an intermediary that intercepts copy commands from the CPU before they reach the system bus. By executing copying operations internally using its buffer and copy logic, the cache prevents unnecessary data traffic from occupying system bus bandwidth, while still allowing the CPU to initiate copying with simple commands.
Solution Approach 2:
The cache performs data copying using its own dedicated copy logic and buffer resources, serving itself rather than relying on external CPU or DMA controller intervention for each data transfer operation. This self-service capability eliminates the need for CPU to occupy system bus bandwidth during copying.
3Productivity
If data copying is performed through system bus using PIO or DMA, then data can be copied, but bus traffic increases and system performance decreases
Solution Approach 1:
The patent introduces a new dimension for data copying by implementing a dedicated copy logic unit within the cache that operates independently from the system bus data path. This alternative copying path allows data to be transferred between memory locations without traversing the system bus, effectively reducing bus traffic while maintaining copying capability.
Data Source
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AI summary
A cache and a method for performing data copying are provided. The cache includes a copy logic and be connected to a processor through a first bus and to a memory controller through a second bus, which is different from the first bus. Moreover, the copy logic may perform data copying through the second bus based on a data copy command received from the processor.