Cache Data Location via Direct Address Translation

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Solution Overview

Problem

Current computer storage systems face bottlenecks in accessing data due to the time-consuming process of identifying the physical location of data within the cache, especially with the advent of higher-speed cache memory, where internal metadata lookups are required for cache data location.

Innovation Solution

The implementation of a direct and faster address translation data structure, such as a hash table, in combination with a multilevel translation index, allows for quicker data access by directly translating block logical addresses to candidate physical addresses and using the multilevel index to update and correct the direct cache address translation data structure when data is moved, ensuring accurate and up-to-date physical locations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If internal metadata lookups are used to locate data on cache, then data location accuracy is maintained, but access time increases significantly

Engineering Contradiction:
Improvedata access timeVSAvoidaddress translation mechanism
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent segments the address translation process into two distinct components: a fast direct address translation data structure for quick candidate location identification, and a multilevel translation index for accurate physical location verification. This segmentation allows the system to benefit from both fast access and accurate location tracking without requiring a single complex metadata lookup mechanism.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary candidate physical address as a bridge between the logical block address and the actual physical location on cache. This intermediary serves as a fast approximation that can be quickly retrieved, then verified against the multilevel translation index to ensure accuracy, thereby reducing overall access time while maintaining location precision.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If direct address translation is used for faster access, then access speed improves, but reliability decreases when data is moved or removed

Engineering Contradiction:
Improveaddress translation speedVSAvoiddata location accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the system first attempts direct address translation to obtain a candidate physical address, then verifies this address against the multilevel translation index. If the data has been moved or removed since the direct translation was created, the verification step detects the discrepancy and triggers an update to the direct address translation data structure, ensuring ongoing reliability.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent performs preliminary direct address translation to obtain a candidate physical address before verifying its validity through the multilevel translation index. This preliminary action provides a fast initial result that is then refined through verification, allowing the system to achieve both speed and reliability by doing the fast operation first and then correcting if necessary.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11226904B2Cache data location system
Publication Date: 2022.01.18 HEWLETT PACKARD ENTERPRISE DEV LP
  • US11226904B2 patent drawing
  • US11226904B2 patent drawing
  • US11226904B2 patent drawing

AI summary

A system may include a persistent storage device, a low latency cache device, a volatile memory; and a processor. The processor is to store a data structure in the volatile memory that is usable to directly translate a block logical address for targeted data to a candidate physical location on the cache device, store a multilevel translation index in the volatile memory for translating the block logical address for the targeted data to an expected physical location of the targeted data on the cache device and attempt accessing the targeted data at the candidate physical location retrieved from the direct cache address translation data structure. In response to the targeted data not being at the candidate physical address, access the targeted data at the expected physical location retrieved from the multilevel translation index.