Delayed Snoop Cache Handling for Multi-Core False Sharing
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Solution Overview
Problem
In multi-core coherent systems, maintaining data coherency and reducing CPU stall overhead while maximizing memory throughput is challenging due to varying cache structures and access patterns among different processor components, leading to bottlenecks in shared memory access.
Innovation Solution
A method is introduced where data blocks are stored in a cache line, with each processor maintaining a local copy and executing child processes to generate output data, allowing for write-through operations and invalidate requests to manage cache coherency, reducing the need for serial snooping and evictions among cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serial snooping and eviction is used to maintain cache coherency in false sharing scenarios, then data consistency is guaranteed, but CPU stall overhead increases and memory throughput decreases
Solution Approach 1:
The patent segments the cache line into multiple data blocks, with each block tracked independently in the snoop filter. This allows the system to identify which specific blocks are modified by different cores, rather than treating the entire cache line as a single unit. When a write occurs, only the specific modified block is invalidated in other cores' caches, not the entire cache line, thereby reducing unnecessary stalls and improving throughput while maintaining consistency.
Solution Approach 2:
The patent implements dynamic tracking of modified data blocks within cache lines using metadata in the snoop filter. The system dynamically updates which blocks are modified by which cores based on actual write operations. This dynamic approach allows the coherency protocol to adapt to the actual access patterns, invalidating only necessary blocks rather than using static conservative invalidation of entire cache lines, thus reducing CPU stall overhead.
2Reliability
If conservative cache invalidation is used to ensure data consistency across cores, then coherency is maintained, but CPU stall overhead increases
Solution Approach 1:
The snoop filter is segmented to track individual data blocks within cache lines separately. Each block has its own validity state and ownership information. This segmentation enables precise invalidation of only the specific blocks that need to be invalidated, rather than conservatively invalidating entire cache lines, thereby reducing CPU stall overhead while maintaining coherency.
Solution Approach 2:
The patent changes the granularity parameter of cache invalidation from cache-line level to data-block level. By tracking and invalidating at the finer block granularity, the system reduces the amount of data that needs to be stalled and re-fetched, thereby reducing CPU stall overhead while maintaining the necessary coherency guarantees.
3Productivity
If different cache structures are used by different processor components, then system heterogeneity and performance are improved, but access bottlenecks and coherency management complexity increase
Solution Approach 1:
The snoop filter is designed as a universal structure that can track data blocks regardless of which processor component (core, DSP, GPU, etc.) accesses them. The same snoop filter infrastructure handles coherency for all heterogeneous components, providing a unified coherency management mechanism that works across different cache structures and access patterns, thereby reducing the complexity of managing coherency in heterogeneous systems.
Data Source
AI summary
Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.