Cache Delta Allocation for Multi-Processor Atomic Operations
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Solution Overview
Problem
In multi-processor systems with shared memory, performing multiple atomic operations on the same memory location leads to performance degradation due to the need for serializing these operations, which causes stalls and increased power consumption as data is ping-ponged between cores, especially in systems with a large number of cores.
Innovation Solution
A hierarchical memory system with cache coherency control circuitry allows processors to allocate storage locations for delta values instead of the actual data item, performing operations on these delta values locally and updating the data item only when necessary, reducing the need for frequent memory access and enabling efficient handling of marked requests that do not require returning a value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If atomic operations are serialized to maintain observable semantics, then atomicity is preserved, but performance degrades significantly with multiple cores
Solution Approach 1:
The atomic operation is segmented into two independent phases: (1) computing the delta value locally in each core's cache without blocking others, and (2) applying the delta to the base value in memory. This segmentation allows parallel execution of delta computations while preserving atomicity in the final result, resolving the contradiction between maintaining atomicity semantics and achieving high throughput with multiple cores.
2Reliability
If data is ping-ponged between cores for atomic operations, then atomicity is maintained, but power consumption increases
Solution Approach 1:
The patent extracts the computationally intensive delta calculation from the shared memory system and performs it locally in each core's private cache. Only the compact delta value (not the entire data structure) needs to be transferred to memory for the final apply operation. This extraction reduces the volume of data ping-ponged between cores and memory, thereby maintaining atomicity while significantly reducing power consumption.
3Reliability
If all memory accesses are blocked during atomic operations, then atomicity is ensured, but system throughput decreases
Solution Approach 1:
The patent introduces dynamic behavior to atomic operations by allowing non-atomic delta computations to proceed in parallel in each core's cache, then dynamically coordinating only at the final apply stage. The memory access pattern transitions from blocked (traditional atomic operations) to non-blocking during delta computation, with coordination happening only when deltas need to be applied. This dynamic approach ensures atomicity integrity while maintaining high memory access throughput throughout the system.
Data Source
AI summary
A processing apparatus comprising: several processors for processing data; a hierarchical memory system comprising a memory accessible to all the processors, and several caches corresponding to each of the processors, each of the caches being accessible to the corresponding processor and comprising storage locations and corresponding indicators. There is also cache coherency control circuitry for maintaining coherency of data stored in the hierarchical memory system. The processors are configured to respond to receipt of a predefined request to perform an operation on a data item to determine if the cache corresponding to the processor receiving the request has a storage location allocated to the data item. If not, the processing apparatus is configured to: allocate a storage location within the cache to the data item, set the indicator corresponding to the storage location to indicate that the storage location is storing a delta value, set data in the allocated storage location to an initial value. The processor is configured in response to the predefined request to perform the operation on data within the storage location allocated to the data item.