Cache Device Parallel Buffer Control for Access Latency
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Solution Overview
Problem
Conventional cache devices experience latency and slower access speeds due to the time required to complete an access request, even when a cache hit occurs, as they do not efficiently manage write and read operations in parallel, leading to inconsistent response times between cache hits and misses.
Innovation Solution
The cache device incorporates multiple buffers (write buffers, read buffer, and write-back buffer) and a control circuit that manages cache operations by determining cache hits or misses, allowing for parallel execution of write and read operations, and using a write-back buffer to reduce response time by storing data in buffers before writing to the cache memory, thereby minimizing the time required for access completion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the cache device waits for the main memory to complete data transfer before responding to the processor, then data consistency is maintained, but the access response time increases
Solution Approach 1:
The patent introduces a buffer that stores data before it is written to the cache memory. When the processor requests data, the buffer can immediately provide the data if it is already stored there, without waiting for the main memory transfer to complete. This preliminary storage action resolves the contradiction by enabling fast response while maintaining data consistency through subsequent buffer-to-cache transfer.
Solution Approach 2:
The buffer acts as an intermediary component between the main memory and the cache memory. It temporarily holds data during transfer, allowing the cache device to respond to processor requests independently of the main memory transfer status. This intermediary structure enables the system to maintain both fast response times and data consistency.
2Reliability
If the cache device processes write requests sequentially, then data integrity is ensured, but the throughput decreases
Solution Approach 1:
The patent divides the write operation into two independent segments: writing to the buffer and writing to the cache memory. These segments can be executed in parallel, with the buffer write happening immediately and the cache write following afterward. This segmentation allows the system to maintain data integrity while significantly improving throughput by eliminating sequential dependencies.
Solution Approach 2:
The buffer continuously accepts and stores incoming data writes without interruption. While one write operation is being processed, the buffer remains ready to accept the next write request, ensuring continuous useful action. This continuity maintains data integrity through proper buffering while maximizing throughput by preventing idle time between operations.
3Device complexity
If the cache device uses a single buffer for both read and write operations, then device complexity is reduced, but access speed decreases due to buffer contention
Solution Approach 1:
The patent separates the buffer into distinct read and write buffers, allowing independent access paths for read and write operations. This segmentation eliminates buffer contention where read and write operations would compete for the same resource, thereby maintaining high access speeds while the overall structure remains relatively simple.
Solution Approach 2:
Each buffer (read buffer and write buffer) is specialized for its specific function, allowing them to operate independently and efficiently. The read buffer is optimized for serving read requests while the write buffer handles write operations, creating a multi-functional system that achieves high performance without excessive complexity.
Data Source
AI summary
A cache device interposed between a processor and a memory device, including: a cache memory storing data from the memory device; a buffer holding output data output from the processor; a control circuit determining, on the basis of a request to access the memory device, whether a cache hit has occurred or not and, if a cache miss has occurred, storing the output data in the buffer in response to the access request, outputting a read request for reading the data in a line containing data requested by the access request from the memory device, storing data output from the line of the memory device into the cache memory, and storing the output data from the buffer into the cache memory.