3D Cache Die Bonding for Low-Latency Mobile Computing
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Solution Overview
Problem
Current semiconductor systems face limitations in achieving high performance with low power consumption, particularly for mobile-oriented chips, due to the inability to provide the required latency and bandwidth for cache operations and limited power reduction through bonding structures.
Innovation Solution
A computing device architecture that includes a first die with a processing unit and cache memory, and a second die with a larger capacity L3 cache, bonded using a C2C bonding method, which reduces latency and increases operating speed by optimizing the storage capacity and operating speed of cache levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a DRAM is used as a last level cache, then storage capacity can be increased, but latency and bandwidth requirements for cache operation cannot be met
Solution Approach 1:
The cache memory is segmented into multiple levels (L1, L2, L3 caches) with different storage capacities and access speeds. The L1 cache provides fast access for frequently used data, while the L3 cache provides larger storage capacity, creating a hierarchical structure that balances speed and capacity requirements
Solution Approach 2:
The patent implements a nested cache hierarchy where L1 cache is nested within the processing device, L2 cache is nested as a separate die bonded to the first die, and L3 cache is nested as another separate die bonded to the second die. This nested structure allows each cache level to serve different purposes in the memory hierarchy
2Loss of energy
If a bonding structure utilizing micro bumps is used, then power consumption can be reduced, but the reduction is insufficient
Solution Approach 1:
The patent combines multiple bonding techniques (micro bumps and wire bonds) in a hybrid bonding structure. The micro bumps provide low-resistance electrical connections for power and ground, while wire bonds provide flexible signal routing, achieving both power reduction and high performance
Solution Approach 2:
Different bonding methods are applied to different regions of the die connections. Micro bumps are used specifically for power and ground connections where low resistance is critical, while wire bonds are used for signal connections where flexibility and routing are important
3Quantity of substance
If cache storage capacity is increased, then more data can be stored, but operating speed may be compromised
Solution Approach 1:
The cache is segmented into multiple bank groups that respectively correspond to multiple channels, allowing parallel access to different data blocks. This segmentation enables the system to maintain high operating speed while providing large storage capacity by servicing multiple requests simultaneously
Data Source
AI summary
A computing device includes a first die that includes a logic structure that includes a processing device that performs computation with respect to data, a front side line structure disposed on a front surface of the logic structure and that includes lines, and a back side power network structure disposed on a back surface of the logic structure and that provides power. The computing device further includes a second die that includes a memory device that stores the data for the computation of the processing device. The memory device includes a plurality of bank groups that respectively correspond to a plurality of channels, and the second die is bonded onto the back side power network structure by a C2C bonding method.