Multi-Core Cache Directory Entry Consolidation

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Solution Overview

Problem

Current cache coherence protocols in multi-core processor systems lead to high storage overheads due to the generation of numerous directory entries, especially when frequent write operations occur, which complicates the management of cache status and sharing status of data blocks.

Innovation Solution

A cache directory processing method that combines directory entries based on access type and sharer, replacing existing directory entries with combined ones when the record quantity is reduced, thereby optimizing on-chip storage space utilization while maintaining accurate sharing status indication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple line directory entries are generated for each data block in an interval when write operations occur, then cache status coherence is maintained, but storage overheads occupied by directory entries increase excessively

Engineering Contradiction:
Improvecache status coherenceVSAvoidstorage overheads
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent combines multiple line directory entries into a single interval directory entry when they share the same access type and sharer. Instead of creating separate directory entries for each data block, the system merges them at the interval level, reducing the total number of directory entries while maintaining cache coherence information.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The interval directory entry serves multiple functions by representing multiple data blocks simultaneously. A single interval directory entry can manage cache status for multiple data blocks within the interval, making the directory structure more efficient and reducing storage overheads.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If a directory structure is used to manage cache coherence, then data sharing is controlled effectively, but on-chip storage space is occupied by the directory structure

Engineering Contradiction:
Improvedata sharing controlVSAvoidon-chip storage space
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent segments the directory structure into interval-based entries rather than individual line entries. By organizing directory entries at the interval level, the system reduces the number of entries needed while maintaining the ability to control data sharing across multiple data blocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple individual directory entries are merged into interval directory entries, reducing the total storage space required on-chip while preserving the functionality of tracking cache coherence and data sharing status.

Inventive Principle:
Principle #5Merging (Combining)

3Quantity of substance

If private interval directory entries are used to indicate cache status, then storage overheads are reduced, but accurate indication of sharing status becomes difficult when multiple processor nodes access data blocks

Engineering Contradiction:
Improvestorage overheadsVSAvoidsharing status indication accuracy
Core Design Contradiction:
Quantity of substanceVSLoss of information

Solution Approach 1:

The patent introduces a sharer field in the interval directory entry that specifically tracks which processor cores have access to the data. This local quality field provides precise sharing status information while maintaining the space efficiency of interval-based entries.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The interval directory entry acts as an intermediary structure that bridges the gap between space efficiency and information accuracy. It provides a condensed representation that maintains essential sharing status information through the sharer field while reducing overall storage requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10216634B2Cache directory processing method for multi-core processor system, and directory controller
Publication Date: 2019.02.26 HUAWEI TECH CO LTD
  • US10216634B2 patent drawing
  • US10216634B2 patent drawing
  • US10216634B2 patent drawing

AI summary

A cache directory processing method for a multi-core processor system, and directory controllers is presented. The method includes obtaining a first directory entry corresponding to first-type storage space in shared storage space of the multi-core processor system and in a directory of the shared storage space; performing a directory entry combination operation on the first directory entry according to each directory entry in the first directory entry and according to an access type and a sharer, to form a second directory entry of the first-type storage space; and when a record quantity of the second directory entry is less than a record quantity of the first directory entry, replacing the first directory entry with the second directory entry, and using the second directory entry as a directory entry corresponding to the first-type storage space and in the directory of the shared storage space.