Distributed Cache Coherency Directory Failure Redundancy
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Solution Overview
Problem
In multi-processor cache coherent systems, the failure of a cache coherency directory renders the entire system unusable, as existing technologies lack redundancy mechanisms to reassign memory addresses and reconfigure processors effectively upon directory failure.
Innovation Solution
A system and method that include directory controllers to identify and reassign memory addresses from a failed cache coherency directory to non-failed directories, with a service processor flushing caches and reconfiguring processors to maintain system operation without requiring a full shutdown or replacement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a distributed cache coherency directory is implemented with multiple separate components, then the system can track memory addresses in a modular way, but the failure of any single component renders the entire system unusable
Solution Approach 1:
The cache coherency directory is divided into multiple separate directory components, each tracking a specific portion of memory addresses. This segmentation allows modular tracking of memory while enabling failure isolation, where one component's failure does not affect others.
Solution Approach 2:
The system pre-configures backup directory components and establishes reassignment protocols before failures occur. When a directory component fails, the system automatically detects the failure and reassigns its tracked memory addresses to surviving components without requiring system shutdown or manual intervention.
2Reliability
If the system shuts down completely upon directory failure to maintain data integrity, then cache coherency is preserved, but system productivity is lost
Solution Approach 1:
The system converts the harmful effect of directory failure into a beneficial opportunity for automatic reconfiguration. Instead of shutting down, the failure triggers automatic detection and reassignment mechanisms that redistribute memory address tracking to surviving directory components, maintaining both coherency integrity and system productivity.
Solution Approach 2:
The system performs self-diagnosis and self-reconfiguration when a directory component fails. The service processor automatically detects the failure, identifies surviving components, reassigns memory addresses, and updates processor configurations without external intervention, allowing continuous operation while preserving cache coherency.
3Reliability
If manual replacement of failed directory components is required, then system reliability can be restored, but loss of time occurs during the replacement process
Solution Approach 1:
The system automatically detects directory component failures and performs reconfiguration without requiring manual intervention. The service processor identifies failed components, reassigns their memory addresses to surviving components, and updates system configurations autonomously, eliminating downtime associated with manual replacement procedures.
Solution Approach 2:
The system maintains continuous operation through automatic failure response mechanisms. When a directory component fails, the system immediately initiates reassignment of memory addresses to surviving components, ensuring uninterrupted system functionality and eliminating idle time during failure handling.
Data Source
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AI summary
A system includes a number of processors with each processor including a cache memory. The system also includes a number of directory controllers coupled to the processors. Each directory controller may be configured to administer a corresponding cache coherency directory. Each cache coherency directory may be configured to track a corresponding set of memory addresses. Each processor may be configured with information indicating the corresponding set of memory addresses tracked by each cache coherency directory. Directory redundancy operations in such a system may include identifying a failure of one of the cache coherency directories; reassigning the memory address set previously tracked by the failed cache coherency directory among the non-failed cache coherency directories; and reconfiguring each processor with information describing the reassignment of the memory address set among the non-failed cache coherency directories.