Segmented Cache Directory Management for Bus Traffic Reduction
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Solution Overview
Problem
In large symmetric multiprocessing computer systems, existing cache management techniques face challenges in maintaining efficient cache coherence and reducing data traffic over bus lines, particularly due to the limitations of shared cache architectures and the need for trade-offs between cache size and connectivity.
Innovation Solution
The implementation of a system where each processor shares a first cache memory and a second cache memory is introduced, allowing for cache line requests to be handled by the first cache memory, which sends requests to a memory controller, creates a directory state, and provides this state to the second cache memory for directory entry creation without transferring data, thereby reducing bus line traffic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a shared cache memory architecture is used among multiple processors, then cache coherence can be maintained, but data traffic over bus lines increases significantly
Solution Approach 1:
The cache memory is segmented into two distinct parts: a first cache memory for storing actual cache lines and a second cache memory for storing only directory states. This segmentation allows the system to maintain cache coherence information separately from data, reducing the amount of data that needs to be transmitted over bus lines when updating directory information.
Solution Approach 2:
The directory state information is extracted from the main cache memory and stored in a separate second cache memory. When directory updates are needed, only the compact directory state information is transferred to the second cache memory, rather than transferring entire cache lines, thereby reducing bus line traffic.
2Productivity
If cache size is increased to improve performance, then more data can be cached, but device complexity and connectivity requirements increase
Solution Approach 1:
The cache system is divided into two functional segments: the first cache memory handles data storage and caching operations, while the second cache memory handles directory state management. This segmentation allows each component to be optimized independently, managing complexity while maintaining large cache capacity for improved performance.
Solution Approach 2:
The patent adds a dimensional separation between data storage (first cache memory) and directory information (second cache memory). This dimensional change allows the system to scale cache size without proportionally increasing the complexity of directory management and connectivity requirements.
3Ease of operation
If directory states are stored in the same cache memory as data, then access is simplified, but bus line traffic increases due to redundant data transfer
Solution Approach 1:
The cache system is segmented into data storage (first cache memory) and directory information (second cache memory). This allows directory states to be updated independently without requiring transfer of redundant data, reducing bus line traffic while maintaining access efficiency through dedicated directory management.
Solution Approach 2:
Instead of transferring actual cache line data to update directory information, the system creates and transfers only the necessary directory state copies to the second cache memory. This copying approach maintains the needed information while minimizing bus line traffic by transferring only essential metadata.
Data Source
AI summary
Methods and systems for cache management are provided. Aspects include providing a drawer including a plurality of clusters, each of the plurality of clusters including a plurality of processor each having one or more cores, wherein each of the one or more cores shares a first cache memory, providing a second cache memory shared among the plurality of clusters, and receiving a cache line request from one of the one or more cores to the first cache memory, wherein the first cache memory sends a request to a memory controller to retrieve the cache line from a memory, store the cache line in the first cache memory, create a directory state associated with the cache line, and provide the directory state to the second cache memory to create a directory entry for the cache line.