Cache Directory Segmentation for Power-Efficient Address Translation
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Solution Overview
Problem
The increasing size of microprocessor core caches leads to higher power consumption and timing constraints, particularly due to the power consumption and size limitations of the Translation Lookaside Buffer (TLB) in translating logical to physical addresses, which slows down cache access times.
Innovation Solution
A method for controlling cache memory access using a logically indexed and tagged directory structure that reduces the need for TLB power-up by employing a set directory for selecting potential hit sets and a vertically stacked validation directory, allowing only one set to be read at once, thus minimizing power and area usage while maintaining fast access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TLB is used for translating logical addresses to physical addresses in cache, then address translation is achieved, but power consumption increases and access time increases
Solution Approach 1:
The patent divides the traditional single TLB structure into two separate directories: a set directory that stores only the upper bits of the logical address, and a validation directory that stores the lower bits and validation information. This segmentation allows the system to perform partial address translation in the set directory without requiring full TLB operation, reducing power consumption while maintaining translation capability.
Solution Approach 2:
The patent implements partial address translation by using only the upper bits of the logical address in the set directory for initial filtering. This partial action eliminates the need to activate the full TLB for every cache access, thereby reducing power consumption while still achieving the necessary address translation function through the combination of set directory filtering and validation directory verification.
2Reliability
If TLB size is increased to handle larger cache, then address translation coverage is improved, but timing constraints are violated and access time increases
Solution Approach 1:
The patent segments the address translation process into two stages: first, the set directory uses upper bits of the logical address to identify potential cache sets; second, the validation directory uses lower bits to confirm the actual cache line. This segmentation enables the system to handle larger cache addresses without increasing the size of either directory individually, maintaining timing constraints while improving address translation coverage.
Solution Approach 2:
The patent introduces a new dimensional approach to address translation by separating the address bits into upper and lower portions and using them in different directories. This dimensional change allows the system to scale to larger caches by distributing address bits across multiple directory structures rather than increasing the size of a single TLB, thereby maintaining fast access times.
3Device complexity
If traditional cache directory structure is used, then implementation is simple, but power consumption is high due to TLB power-up
Solution Approach 1:
The patent segments the traditional cache directory into two independent directories: set directory and validation directory. This segmentation allows the system to activate only the set directory for initial filtering operations, avoiding the need to power-up the entire TLB structure. The validation directory is activated only when needed, significantly reducing overall power consumption while maintaining directory functionality.
Solution Approach 2:
The patent implements a dynamic directory structure where the set directory and validation directory can be independently activated based on the specific cache access requirements. This dynamic approach allows the system to adjust power consumption by activating only the necessary directory components for each access operation, rather than maintaining the traditional static TLB power-up state.
Data Source
AI summary
Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.