Cache Directory Selective Listing for Eviction Reduction
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Solution Overview
Problem
In multiprocessor systems, the large number of communication requirements for cache coherence and the frequent eviction operations, particularly affecting pre-loading of instructions, lead to delays and inefficiencies due to the need for regular updates in proxy module directories, which become cumbersome as the number of processors increases.
Innovation Solution
A cache coherence management module that selectively lists only addresses associated with exclusive data states, avoiding the listing of shared data, thereby reducing the need for evictions and optimizing directory space usage by not storing 'shared' or 'invalid' state data in the directory, allowing for reduced updates and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the directory lists all cache memory addresses including shared data, then the directory provides complete information for cache coherence management, but the directory size increases and requires frequent eviction operations
Solution Approach 1:
The patent extracts shared data entries from the directory listing, maintaining only exclusive and invalid entries. This selective extraction reduces directory size and eviction frequency while preserving cache coherence functionality, as shared data can be managed through other mechanisms without requiring directory entries.
Solution Approach 2:
Instead of maintaining a complete directory of all cache entries, the patent applies partial action by listing only necessary entries (exclusive and invalid states). This partial listing is sufficient for maintaining cache coherence while significantly reducing directory overhead and eviction operations.
2Reliability
If the directory is frequently updated to maintain cache coherence, then cache consistency is ensured, but system performance decreases due to update overhead
Solution Approach 1:
By extracting shared data entries from the directory, the patent eliminates unnecessary update operations for shared data. This reduces the frequency of directory updates and evictions while maintaining cache consistency, thereby improving system performance.
Solution Approach 2:
The patent changes the parameter of directory content by selectively including only exclusive and invalid entries rather than all cache entries. This parameter change reduces the directory update frequency and overhead, improving system performance while maintaining cache coherence.
3Device complexity
If eviction operations are performed frequently to manage directory space, then directory size is controlled, but program execution speed decreases due to delays
Solution Approach 1:
The patent extracts shared data entries from the directory, preventing them from being subject to eviction operations. This eliminates eviction-related delays for shared data while maintaining directory space control through selective listing of only exclusive and invalid entries.
4Reliability
If the directory maintains complete information about all processors and data, then cache coherence is accurately tracked, but the number of communication requirements increases
Solution Approach 1:
The patent extracts shared data entries from the directory, reducing the amount of information that requires communication and updates. This reduces communication overhead while maintaining accurate tracking of cache coherence for exclusive and invalid entries through the simplified directory structure.
Data Source
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AI summary
Directory-based cache consistency management module, wherein each data stored in cache memory is associated with a state, at least one of which state reflects data sharing between several processors comprising: - a storage unit to store a directory containing a list of cache memory addresses, each address being able to be associated with a state corresponding to the state of the data available at that address, and - a processing unit configured to update said list, said processing unit being configured not to list address lines relating to data associated with said first state.