Cache Dirty-Data Scheduling for Low-Latency Memory Access
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Solution Overview
Problem
The inefficiency in memory access due to high read/write switching times and delays in read commands, particularly in systems with limited queue depth and cache capability, affects the performance of processors.
Innovation Solution
A cache system that actively sends dirty data to the memory controller before cache lines are allocated to new memory addresses, optimizing the scheduling of read/write commands to reduce switching times and delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the memory controller performs read/write scheduling with a small internal queue depth, then the device complexity is reduced, but the productivity of memory access decreases due to frequent read/write switching
Solution Approach 1:
The patent divides the memory access system into two independent scheduling entities: the memory controller with its small internal queue for read commands, and the cache with its own write command queue. This segmentation allows each component to operate independently with optimized queue depths, avoiding the need for a large centralized queue while reducing read/write switching overhead through coordinated scheduling between the two segments.
Solution Approach 2:
The cache acts as an intermediary between the processor and memory, taking on additional scheduling responsibilities. It maintains a write command queue and actively manages dirty data, mediating between write commands from the processor and the memory controller's read command schedule. This intermediary role enables the memory controller to maintain a small queue depth while the cache handles write scheduling independently.
2Device complexity
If the cache passively sends dirty data to the memory controller after cache line allocation, then the device complexity is reduced, but the productivity decreases due to uncontrolled sending occasions leading to more read/write switching
Solution Approach 1:
The cache performs preliminary actions by proactively sending dirty data to the memory controller before cache lines are allocated to new memory addresses. This advance action allows the memory controller to schedule write commands in advance, coordinating them with read command execution. By taking preliminary action rather than waiting for passive triggers, the system reduces the number of read/write switching events and improves memory access efficiency.
Solution Approach 2:
The cache implements a feedback mechanism by monitoring its own state (dirty cache lines) and the memory controller's schedule, then actively deciding when to send dirty data. This feedback-driven active sending occasions allow the cache to coordinate with the memory controller's read command schedule, sending dirty data at optimal times that minimize read/write switching and maximize memory access efficiency.
3Productivity
If the read command execution is delayed to allow dirty data writing, then the productivity of memory writing is improved, but the speed of read data access decreases
Solution Approach 1:
The system implements dynamic scheduling where the memory controller and cache continuously adapt their command issuance based on real-time conditions. The cache dynamically determines when to send dirty data based on its dirty cache line count and the memory controller's read schedule. The memory controller dynamically adjusts its read command timing based on incoming write commands from the cache. This dynamic coordination allows the system to optimize for either read speed or write efficiency depending on the current workload, rather than being constrained by fixed timing.
Data Source
AI summary
Embodiments of this disclosure provide a cache, a control method therefor, and a computer system, and relate to the field of storage technologies, to improve memory access efficiency of the computer system. The cache is connected to a memory controller, and the cache includes a plurality of cache lines. The control method for a cache includes: storing write data of a received write command into cache lines, and before the cache lines are allocated to new memory addresses, sending dirty data stored in the cache lines to the memory controller.