Cache Dirty Data Eviction via Notification Sorter
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Solution Overview
Problem
The existing memory management systems face inefficiencies in determining which data to transmit from an intermediate cache, such as an L2 cache, to an external memory, leading to performance issues due to excessive retrieval from DRAM, which impacts overall system performance.
Innovation Solution
A method is introduced that involves receiving a dirty data notification, extracting the bank page number from the memory address, and incrementing a count associated with the notification sorter to prioritize the eviction of cache lines with dirty data belonging to the evict_first data class, ensuring they are cleaned before other data classes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of write operations to DRAM bank page is maximized, then memory access efficiency is improved, but data may be evicted from L2 cache before reuse, increasing cache misses
Solution Approach 1:
The patent changes the parameter of eviction priority by introducing data class tags (evict_first, evict_normal, evict_last) and using count thresholds to dynamically adjust which data gets evicted. This allows the system to prioritize evicting certain data classes over others based on current cache state and access patterns, resolving the contradiction between maximizing writes and maintaining data reuse.
Solution Approach 2:
The patent implements feedback mechanisms through count thresholds that monitor the number of dirty data notifications per bank page. When counts exceed thresholds, the system adjusts eviction behavior accordingly. This feedback loop allows the system to adaptively balance between flushing data to DRAM and retaining data in L2 cache for potential reuse.
2Reliability
If data is retained in L2 cache longer for reuse, then cache hit rate is improved, but write operations to DRAM are delayed, reducing memory throughput
Solution Approach 1:
The patent introduces data class parameters (evict_first, evict_normal, evict_last) that control retention time and eviction priority. By assigning different classes to different data, the system can retain some data longer (improving cache hit rate) while actively evicting other data classes to DRAM (maintaining memory throughput), thus resolving the contradiction.
Solution Approach 2:
The patent segments dirty data into different classes based on eviction priority. This segmentation allows the system to handle different data types differently - some data is evicted aggressively while other data is retained longer, enabling simultaneous optimization of cache hit rate and memory throughput through differentiated policies.
3Productivity
If dirty data is evicted aggressively to DRAM, then cache space is freed for new data, but read performance deteriorates due to increased cache misses
Solution Approach 1:
The patent uses eviction priority parameters (evict_first, evict_normal, evict_last) to control which data is evicted and when. By adjusting these parameters based on data class and current cache state, the system can free cache space efficiently while protecting frequently accessed data from aggressive eviction, thus maintaining read performance while improving cache utilization.
Data Source
AI summary
A method for cleaning dirty data in an intermediate cache is disclosed. A dirty data notification, including a memory address and a data class, is transmitted by a level 2 (L2) cache to frame buffer logic when dirty data is stored in the L2 cache. The data classes may include evict first, evict normal and evict last. In one embodiment, data belonging to the evict first data class is raster operations data with little reuse potential. The frame buffer logic uses a notification sorter to organize dirty data notifications, where an entry in the notification sorter stores the DRAM bank page number, a first count of cache lines that have resident dirty data and a second count of cache lines that have resident evict_first dirty data associated with that DRAM bank. The frame buffer logic transmits dirty data associated with an entry when the first count reaches a threshold.