Cache Memory Dynamic Associativity Mapping Security

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Solution Overview

Problem

Cache memories face challenges in achieving both high performance and security due to high miss rates, power inefficiency, and vulnerability to information leakage attacks, which compromise other design goals like reliability and performance.

Innovation Solution

A cache memory system with dynamic memory-to-cache mapping using an address decoder that receives a context identifier and index bits to determine matching values in line number registers, allowing for secure and efficient data retrieval by comparing tags and replacing data lines dynamically, thereby enhancing security and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If direct-mapped cache memory is used to achieve short access times, then access time is improved, but miss rate increases

Engineering Contradiction:
Improveaccess timeVSAvoidmiss rate
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements dynamic associativity where cache sets can operate in different associativity modes (direct-mapped, 2-way set-associative, 4-way set-associative) based on runtime conditions. The cache controller dynamically selects the associativity level for different cache sets, allowing the system to optimize between access time and miss rate adaptively rather than being fixed in one configuration.

Inventive Principle:
Principle #15Dynamics

2Reliability

If fully associative or set-associative cache memory is used to achieve low miss rates, then miss rate is improved, but access time and power consumption increase

Engineering Contradiction:
Improvemiss rateVSAvoidaccess time
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent implements dynamic associativity where cache sets can operate in different associativity modes (direct-mapped, 2-way set-associative, 4-way set-associative) based on runtime conditions. The cache controller dynamically selects the associativity level for different cache sets, allowing the system to optimize between access time and miss rate adaptively rather than being fixed in one configuration.

Inventive Principle:
Principle #15Dynamics

3Reliability

If fully associative or set-associative cache memory is used to achieve low miss rates, then miss rate is improved, but power consumption increases

Engineering Contradiction:
Improvemiss rateVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic associativity where cache sets can operate in different associativity modes (direct-mapped, 2-way set-associative, 4-way set-associative) based on runtime conditions. The cache controller dynamically selects the associativity level for different cache sets, allowing the system to optimize between access time and miss rate adaptively rather than being fixed in one configuration.

Inventive Principle:
Principle #15Dynamics

4Productivity

If cache memory is used to improve processing speed, then productivity is improved, but vulnerability to information leakage attacks increases

Engineering Contradiction:
Improveprocessing speedVSAvoidinformation leakage vulnerability
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent implements dynamic associativity where cache sets can operate in different associativity modes (direct-mapped, 2-way set-associative, 4-way set-associative) based on runtime conditions. The cache controller dynamically selects the associativity level for different cache sets, allowing the system to optimize between access time and miss rate adaptively rather than being fixed in one configuration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of cache associativity dynamically based on workload characteristics and security requirements. By adjusting the associativity level, the system can modify cache behavior to reduce information leakage vulnerability while maintaining acceptable performance levels.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9864703B2Cache memory having enhanced performance and security features
Publication Date: 2018.01.09 CORESECURE TECH LLC
  • US9864703B2 patent drawing
  • US9864703B2 patent drawing
  • US9864703B2 patent drawing

AI summary

A cache memory having enhanced performance and security feature is provided. The cache memory includes a data array storing a plurality of data elements, a tag array storing a plurality of tags corresponding to the plurality of data elements, and an address decoder which permits dynamic memory-to-cache mapping to provide enhanced security of the data elements, as well as enhanced performance. The address decoder receives a context identifier and a plurality of index bits of an address passed to the cache memory, and determines whether a matching value in a line number register exists. The line number registers allow for dynamic memory-to-cache mapping, and their contents can be modified as desired. Methods for accessing and replacing data in a cache memory are also provided, wherein a plurality of index bits and a plurality of tag bits at the cache memory are received. The plurality of index bits are processed to determine whether a matching index exists in the cache memory and the plurality of tag bits are processed to determine whether a matching tag exists in the cache memory, and a data line is retrieved from the cache memory if both a matching tag and a matching index exist in the cache memory. A random line in the cache memory can be replaced with a data line from a main memory, or evicted without replacement, based on the combination of index and tag misses, security contexts and protection bits. User-defined and/or vendor-defined replacement procedures can be utilized to replace data lines in the cache memory.