Processor Cache ECC Logic Using Reusable Common Check Bits

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Solution Overview

Problem

Processor caches with different error correction code (ECC) schemes face challenges in efficiently exchanging and utilizing check bits due to incompatibility, leading to increased computational requirements and power consumption.

Innovation Solution

Implementing compatible check bit generation and confirmation logic between ECC schemes allows for the reuse of common check bits across caches, reducing the need for regenerating check bits during data transfer and enhancing error detection and correction capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If different ECC schemes are used in caches at different levels, then error correction capability is improved, but check bit compatibility deteriorates

Engineering Contradiction:

Improveerror correction capabilityVSAvoidcheck bit compatibility

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The check bits are segmented into two distinct parts: common check bits that are compatible across different ECC schemes and cache levels, and cache-specific check bits that provide enhanced error correction for individual caches. This segmentation allows check bits to be reused across cache levels while maintaining the ability to provide differentiated error protection where needed.

Inventive Principle:

Principle #1Segmentation

2Measurement precision

If check bits are regenerated during data transfer between caches, then error detection accuracy is improved, but computational load increases

Engineering Contradiction:

Improveerror detection accuracyVSAvoidcomputational load

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

Common check bits are generated in advance at the source cache and attached to data before transfer. The destination cache can directly utilize these pre-generated check bits for error detection without needing to regenerate them, thereby reducing computational load while maintaining error detection capability.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If check bits are transmitted between caches, then error detection capability is improved, but power consumption increases

Engineering Contradiction:

Improveerror detection capabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The common check bits serve multiple functions: they provide error detection capability during data transfer between caches, and they can be reused by the destination cache for error detection without requiring additional check bit generation or transmission. This multi-functionality reduces the need for separate error detection mechanisms, thereby lowering power consumption.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8533572B2Error correcting code logic for processor caches that uses a common set of check bits

Publication Date: 2013.09.10 SK HYNIX NAND PRODUCT SOLUTIONS CORP

AI summary

A processor or other apparatus of an aspect may include a first cache, a first error correction code (ECC) logic for the first cache, a second cache, and a second ECC logic for the second cache. The apparatus may also include an interconnect coupled with or between the first cache and the second cache. The interconnect is operable to transmit data and also check bits corresponding to the data between the first cache and the second cache. A method of an aspect may include accessing data, and check bits corresponding to the data, from a first cache. The data and the check bits may be transmitted over an interconnect from the first cache to a second cache. The data and the check bits may be stored in the second cache. Other methods, apparatus, and systems are also disclosed.