Cache Memory ECC Layout for Low-Latency Critical Data Access
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Solution Overview
Problem
The 'memory wall problem' in processor performance and power consumption is exacerbated by the increased leakage current in cache memories, and MRAMs, while offering lower leakage current, suffer from higher bit error frequencies, necessitating error correction that prolongs memory access latency due to the need for ECC circuitry to generate redundant codes for each cache line.
Innovation Solution
A cache memory system with separate storage for first and second redundant codes, where the second redundant code is used for error detection of critical data, allowing for parallel or sequential error correction with the first redundant code, enabling quick transfer of corrected critical data to the processor core, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If MRAM is used as cache memory to reduce leakage current, then power consumption is reduced, but bit error frequency increases
Solution Approach 1:
The patent divides the error correction mechanism into two segments: a first redundant code for error correction and a second redundant code for error detection. This segmentation allows the system to handle errors more efficiently by detecting errors with the second code and correcting them with the first code, thereby improving reliability without significantly increasing power consumption.
Solution Approach 2:
The patent performs preliminary error detection using the second redundant code before full error correction is needed. By detecting errors early with the simpler second code, the system can prepare for correction without waiting for the more complex first code processing, thus improving reliability while managing power consumption.
2Reliability
If ECC circuitry is added to correct bit errors in MRAM, then reliability is improved, but memory access latency increases
Solution Approach 1:
The patent segments the redundant code into two parts: a first redundant code for error correction and a second redundant code for error detection. This allows the system to quickly detect errors using the second code without immediately invoking the more time-consuming correction process, thereby reducing latency while maintaining reliability.
Solution Approach 2:
The patent applies partial error correction by using the second redundant code for detection and only invoking full correction with the first code when necessary. This partial approach reduces the average time required for error handling while still ensuring data integrity, thus reducing latency without compromising reliability.
3Productivity
If cache line length is increased to improve memory capacity, then productivity is improved, but error correction time increases
Solution Approach 1:
The patent divides the error correction task into two segments: error detection using the second redundant code and error correction using the first redundant code. This segmentation allows the system to quickly identify errors in longer cache lines without immediately performing time-consuming correction, thus maintaining productivity while reducing error correction time.
Solution Approach 2:
The patent performs preliminary error detection across the entire cache line using the second redundant code before initiating correction with the first code. This preliminary action allows the system to handle errors in long cache lines more efficiently by preparing detection results first, thereby maintaining high memory capacity while reducing overall error correction time.
Data Source
AI summary
A cache memory includes cache memory circuitry that is accessible per cache line and a redundant-code storage that stores one or more numbers of first redundant codes to be used for error correction of cache line data stored in the cache memory circuitry per cache line and one or more numbers of second redundant codes to be used for error detection of a part of the cache line data.