Cache ECC Verification for Non-Correctable Error Handling
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Solution Overview
Problem
Existing memory systems face challenges in efficiently managing non-correctable errors in multi-level cache hierarchies, leading to potential system failures due to soft errors caused by random radiation flipping bits, which current error correcting codes (ECC) may not adequately address.
Innovation Solution
Implementing a controller that manages error correcting codes (ECC) across different memory levels, including calculating current ECC values, comparing stored ECC values, and determining whether to access the first memory based on the presence of non-correctable errors to prevent system access and maintain functional safety.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correcting codes (ECC) are used to detect and correct soft errors in memory systems, then reliability is improved, but non-correctable errors can still cause system failures
Solution Approach 1:
The patent performs preliminary ECC verification by calculating current ECC values and comparing them with stored ECC values before allowing memory access. This preliminary check identifies non-correctable errors in advance, preventing them from propagating to the CPU and causing system failures.
Solution Approach 2:
The patent introduces an intermediary verification mechanism between the L2 cache and L1 cache that acts as a mediator to check data integrity. The ECC verification unit serves as an intermediary layer that filters out non-correctable errors before they reach the CPU, enhancing overall system reliability.
2Measurement precision
If ECC verification is performed for every memory access, then error detection capability is improved, but access speed deteriorates
Solution Approach 1:
The patent applies partial verification by performing ECC checks selectively rather than for every single memory access. The system verifies data integrity at critical points in the memory hierarchy (L2 to L1 cache transfer) rather than at every access point, maintaining error detection capability while minimizing speed impact.
Solution Approach 2:
ECC verification is performed preliminarily during data transfer from L2 to L1 cache, before the actual CPU access occurs. This preliminary verification ensures that only verified data is cached and subsequently accessed, reducing the need for re-verification during actual CPU operations.
Data Source
AI summary
An example device includes a first memory that store a first set of data; a second memory that stores a second set of data that includes a stored error correcting code (ECC) value; and a controller coupled to the first memory and to the second memory. The controller operates to receive a transaction directed to the first set of data, and based on the transaction perform the following operations: retrieve the second set of data from the second memory; calculate a current ECC value based on the second set of data as retrieved from the second memory; compare the stored ECC value to the current ECC value to determine whether the second set of data includes an error; determine whether the error is correctable; and determine not to access the first memory to perform the transaction based on a determination that the second set of data includes the non-correctable error.