Cache ECC Handling for Early Non-Correctable Error Termination
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory systems face challenges in efficiently managing error correcting codes (ECC) across different levels of cache hierarchies, particularly in handling non-correctable errors, which can lead to performance issues and increased latency.
Innovation Solution
The implementation of a cache subsystem that includes a controller capable of transforming single-error correction, double-error detection (SECDED) ECC syndromes to single-error detection (SED) ECC syndromes, allowing for concurrent execution of ECC scrubbing and functional transactions, and terminating transactions early upon detection of non-correctable errors to prevent unnecessary memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC scrubbing transactions are executed sequentially with functional transactions, then error detection and correction is ensured, but system productivity and access speed deteriorate due to increased latency
Solution Approach 1:
The patent implements concurrent execution of ECC scrubbing transactions and functional transactions within the cache subsystem. The controller allows multiple transaction types to proceed simultaneously rather than sequentially, maintaining continuous useful action while ensuring error detection and correction through parallel scrubbing operations.
Solution Approach 2:
The patent performs preliminary ECC syndrome transformation and error detection before functional transactions complete. By pre-calculating ECC syndromes and detecting errors in advance, the system can terminate transactions early when errors are found, preventing wasted processing time and maintaining high productivity.
2Measurement precision
If full ECC verification is performed for all transactions, then measurement precision of error detection is improved, but device complexity and processing overhead increase
Solution Approach 1:
The patent applies different ECC verification strategies to different transaction types and cache levels. L2 cache uses SECDED (single-error correction, double-error detection) while L1 cache uses SED (single-error detection). The controller adapts verification depth based on transaction type, applying full verification only where necessary rather than uniformly to all transactions.
Solution Approach 2:
The patent implements partial ECC verification by performing syndrome transformation and error detection only when necessary. The controller can terminate transactions early upon detecting non-correctable errors, avoiding complete verification of all data when errors are found early in the process.
3Productivity
If transactions are allowed to complete fully, then data access throughput is maintained, but energy consumption increases due to unnecessary processing of erroneous data
Solution Approach 1:
The patent performs preliminary error detection through ECC syndrome calculation and comparison before transactions complete. When non-correctable errors are detected early in the transaction process, the controller terminates the transaction immediately, preventing unnecessary processing and energy consumption associated with completing transactions on erroneous data.
Data Source
AI summary
An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to receive a transaction from a master, the transaction directed to the first memory and comprising an address; re-calculate an error correcting code (ECC) for a line of data in the second memory associated with the address; determine that a non-correctable error is present in the line of data in the second memory based on a comparison of the re-calculated ECC and a stored ECC for the line of data; and in response to the determination that a non-correctable error is present in the line of data in the second memory, terminate the transaction without accessing the first memory.