Cache ECC Scrubbing with Parallel Functional Transactions
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Solution Overview
Problem
Current memory systems face challenges in maintaining adequate functional safety due to soft errors and transient faults, particularly in multi-level cache systems where error correcting codes (ECC) need to be managed across heterogeneous interfaces and varying protection levels, leading to complexities in ensuring reliable data integrity and performance.
Innovation Solution
The implementation of a central processing unit (CPU) core with a cache subsystem that includes a memory configured to store data and ECC syndromes, where a controller transforms ECC syndromes from single-error correction, double-error detection (SECDED) to single-error detection (SED) and executes scrubbing transactions concurrently with functional transactions, allowing for early termination of transactions with non-correctable errors to maintain data integrity and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC scrubbing transactions are executed sequentially with functional transactions, then data integrity is maintained through error correction, but system performance and latency are degraded due to sequential processing
Solution Approach 1:
The memory system is divided into multiple memory banks that can be independently accessed. The controller segments the scrubbing operation to execute only on specific banks that require error correction, while allowing functional transactions to proceed in parallel on other banks. This segmentation enables concurrent execution of scrubbing and functional transactions, improving overall system performance while maintaining data integrity through targeted error correction.
2Measurement precision
If ECC syndromes are transformed and calculated for every transaction, then error detection accuracy is improved, but power consumption and processing time increase
Solution Approach 1:
ECC syndromes are pre-calculated and stored with data during write operations. When a read or scrubbing transaction occurs, the controller retrieves the pre-calculated syndrome and performs transformation only when necessary (e.g., when changing ECC types or performing scrubbing). This preliminary calculation approach maintains error detection accuracy while significantly reducing the power consumption and processing time associated with repeated syndrome calculations.
Solution Approach 2:
The controller performs partial syndrome transformation only for the portions of data that require ECC type conversion or scrubbing, rather than processing entire memory blocks. This selective approach maintains error detection accuracy for affected regions while minimizing unnecessary power consumption from processing unaffected data.
3Adaptability or versatility
If the system uses heterogeneous ECC interfaces with different protection levels, then compatibility with various masters is improved, but device complexity increases
Solution Approach 1:
The controller acts as an intermediary layer between masters with different ECC requirements and the underlying memory system. It provides a unified interface that translates between different ECC types (e.g., SECDED, SED, parity) and manages error correction uniformly. This intermediary approach enables compatibility with heterogeneous masters while abstracting away the complexity of managing multiple ECC schemes, as the controller handles all ECC transformations and error correction operations centrally.
Data Source
AI summary
An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to execute a sequence of scrubbing transactions on the first memory and execute a functional transaction on the second memory. One of the scrubbing transactions and the functional transaction are executed concurrently.