Cache ECC Recalculation for Early Uncorrectable Error Aborts
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Solution Overview
Problem
Current memory systems face challenges in maintaining adequate functional safety due to soft errors and transient faults, particularly in multi-level cache systems where error correcting codes (ECC) need to be managed across different levels of memory hierarchies with varying ECC protection requirements.
Innovation Solution
The implementation of a central processing unit (CPU) core with a cache subsystem that includes a memory configured to store data and ECC syndromes, where the ECC syndromes are calculated and transformed as needed to support single-error correction and double-error detection (SECDED) or single-error detection (SED) ECC, along with a controller that executes scrubbing transactions and functional transactions concurrently to maintain ECC integrity and terminate transactions with non-correctable errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC scrubbing transactions are executed to maintain error detection and correction capability, then reliability is improved, but productivity deteriorates due to additional processing overhead
Solution Approach 1:
The patent implements ECC scrubbing transactions that proactively detect and correct errors in cache lines before they are accessed by functional transactions. By performing preliminary error checking and correction on cache lines stored in the cache subsystem, the system prevents errors from propagating to functional transactions, thereby maintaining high reliability without significantly impacting productivity. The scrubbing operation prepares data in advance, ensuring error-free data is available when needed.
2Productivity
If the controller executes both scrubbing and functional transactions concurrently, then productivity is improved through better resource utilization, but device complexity increases
Solution Approach 1:
The patent divides the cache subsystem into multiple independent cache lines, each with its own ECC syndrome. The controller can independently process scrubbing transactions for different cache lines while simultaneously handling functional transactions for other cache lines. This segmentation allows concurrent execution of scrubbing and functional transactions without requiring complex coordination logic, as each cache line can be processed independently. The modular structure enables parallel operation, improving productivity while keeping controller complexity manageable.
3Reliability
If ECC syndromes are stored for all cache lines to enable comprehensive error correction, then reliability is improved, but loss of substance increases due to additional memory resources required
Solution Approach 1:
The patent implements dynamic ECC syndrome management where the presence and type of ECC protection for each cache line can be changed based on system needs. The controller can selectively enable or disable ECC syndromes for different cache lines, and can transform between different ECC types (e.g., SECDED to SED) depending on the specific requirements of each cache line. This parameter flexibility allows the system to optimize the balance between reliability and resource usage, applying comprehensive error correction only where necessary while reducing overhead in other areas.
Data Source
AI summary
An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to receive a transaction from a master, the transaction directed to the first memory and comprising an address; re-calculate an error correcting code (ECC) for a line of data in the second memory associated with the address; determine that a non-correctable error is present in the line of data in the second memory based on a comparison of the re-calculated ECC and a stored ECC for the line of data; and in response to the determination that a non-correctable error is present in the line of data in the second memory, terminate the transaction without accessing the first memory.