Cache ECC Syndrome Conversion for Multi-Master Memory Access
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Solution Overview
Problem
Current memory systems face challenges in efficiently managing error correcting codes (ECC) across different levels of cache hierarchies, particularly in handling non-correctable errors, which can lead to performance issues and increased latency.
Innovation Solution
The implementation of a cache subsystem with a controller that calculates and transforms ECC syndromes, allowing for concurrent execution of scrubbing and functional transactions, and the ability to terminate transactions early upon detecting non-correctable errors, thereby preventing unnecessary memory access and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory system performs ECC scrubbing transactions sequentially with functional transactions, then error detection and correction is ensured, but system productivity and access speed deteriorate due to increased latency
Solution Approach 1:
The patent implements preliminary ECC scrubbing by performing error detection and correction on cache lines before they are accessed by functional transactions. The scrubbing operation proactively identifies and corrects errors in advance, so when functional transactions occur, the data is already verified and ready for use, eliminating the need to wait for sequential scrubbing completion.
Solution Approach 2:
The patent dynamically adjusts the execution of scrubbing and functional transactions based on system conditions. The controller can interleave scrubbing operations with functional transactions, allowing the system to switch between error correction mode and normal operation mode flexibly, thereby maintaining both reliability and productivity without fixed sequential constraints.
2Productivity
If the memory system continues executing transactions after detecting non-correctable errors, then productivity is maintained, but harmful factors increase due to unnecessary memory access and power consumption
Solution Approach 1:
The patent extracts the harmful continuation of transactions after error detection by implementing an early termination mechanism. When non-correctable errors are detected during scrubbing, the controller immediately stops subsequent functional transactions that would access the erroneous cache lines, removing the source of unnecessary power consumption and memory access before they can occur.
Solution Approach 2:
The patent converts the potentially harmful effect of continued transaction execution into a benefit by using error detection as a trigger for intelligent transaction termination. The detection of non-correctable errors is transformed into a useful signal that prevents wasteful memory accesses and reduces power consumption, turning what could be a system failure point into an energy-saving opportunity.
3Adaptability or versatility
If the memory system transforms ECC syndromes between different types, then adaptability to different masters is improved, but device complexity increases due to additional transformation logic
Solution Approach 1:
The patent implements a universal ECC controller that can handle multiple ECC types (SECDED and SED) and perform syndrome transformations between them. The controller is designed with multi-functional capability to work with different master requirements, allowing the same hardware block to adapt to various ECC schemes without requiring separate dedicated circuits for each type.
Solution Approach 2:
The patent introduces an intermediary ECC transformation layer between the memory subsystem and different masters. This intermediary component receives syndromes from the memory, transforms them between different ECC types as needed, and presents the appropriate syndrome format to each master, thereby simplifying the interface requirements and reducing overall system complexity.
4Productivity
If the memory system accesses memory to complete all transactions, then productivity is maintained, but use of energy increases due to unnecessary memory access after error detection
Solution Approach 1:
The patent performs preliminary error detection during scrubbing operations before functional transactions access the memory. By identifying non-correctable errors in advance, the system can prevent subsequent functional transactions from accessing erroneous cache lines, thereby avoiding unnecessary memory access and the associated power consumption while maintaining transaction completion for healthy data.
Solution Approach 2:
The patent extracts and removes the energy-wasting memory access operations by implementing early termination logic. When errors are detected, the controller extracts the problematic transactions from the execution queue and prevents them from proceeding to memory access, thereby eliminating the harmful power consumption associated with accessing corrupted data while preserving productive transactions.
Data Source
AI summary
An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a memory configured to store a line of data and an error correcting code (ECC) syndrome associated with the line of data, where the ECC syndrome is calculated based on the line of data and the ECC syndrome is a first type ECC. The cache subsystem also includes a controller configured to, in response to a request from a master configured to implement a second type ECC, the request being directed to the line of data, transform the first type ECC syndrome for the line of data to a second type ECC syndrome send a response to the master. The response includes the line of data and the second type ECC syndrome associated with the line of data.