Cache ECC Transformation for Multi-Master Memory Transactions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory systems face challenges in maintaining adequate functional safety due to the complexities of error correcting codes (ECC) across different memory levels, particularly in handling soft errors and non-correctable errors, which can lead to system failures and performance issues.
Innovation Solution
The implementation of a cache subsystem with a controller that calculates and transforms ECC syndromes, including SECDED and SED ECC, to manage and correct errors, and executes scrubbing transactions concurrently with functional transactions, allowing for early termination of transactions with non-correctable errors to prevent further access and reduce latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory system implements multiple ECC types (SECDED and SED) across different memory levels, then the functional safety and error correction capability are improved, but the device complexity and difficulty of managing ECC syndromes increase
Solution Approach 1:
The patent introduces an intermediary ECC syndrome transformation mechanism that converts between different ECC types (SECDED to SED). This intermediary layer allows the memory system to maintain multiple ECC types for different safety requirements while providing a unified interface for error management, thereby reducing the complexity of handling multiple ECC syndromes directly.
Solution Approach 2:
The memory controller is designed with multi-functionality to handle both SECDED and SED ECC types, as well as perform syndrome transformation between them. This universal approach allows a single controller to manage diverse ECC requirements across different memory levels, reducing overall system complexity compared to having separate controllers for each ECC type.
2Reliability
If the system performs ECC scrubbing transactions to correct soft errors, then the reliability is improved, but the latency and power consumption increase due to additional memory access operations
Solution Approach 1:
The system performs ECC scrubbing transactions as preliminary actions to detect and correct soft errors before they affect normal memory operations. By proactively scrubbing memory data and correcting errors in advance, the system prevents future failures without causing latency during normal read/write operations, as corrections are completed beforehand.
Solution Approach 2:
The ECC scrubbing mechanism operates continuously in the background during idle periods or alongside non-critical operations, maintaining continuous error protection without interrupting the main functional transactions. This continuous action ensures reliability while minimizing impact on performance by utilizing otherwise idle time slots.
3Productivity
If the controller continues to process transactions after detecting non-correctable errors, then the productivity is maintained, but the system reliability deteriorates due to potential propagation of corrupted data
Solution Approach 1:
When a non-correctable error is detected, the controller extracts or removes the corrupted transaction from further processing. Instead of continuing to process potentially corrupted data, the system isolates the error by terminating the affected transaction and preventing it from propagating to other system components, thereby maintaining reliability while allowing other healthy transactions to continue processing.
Solution Approach 2:
The system applies preliminary anti-action by detecting non-correctable errors and immediately terminating transactions before corrupted data can be propagated to other memory locations or processing stages. This preemptive termination prevents the spread of errors while the controller can continue handling other valid transactions, thus maintaining overall productivity.
Data Source
AI summary
An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a memory configured to store a line of data and an error correcting code (ECC) syndrome associated with the line of data, where the ECC syndrome is calculated based on the line of data and the ECC syndrome is a first type ECC. The cache subsystem also includes a controller configured to, in response to a request from a master configured to implement a second type ECC, the request being directed to the line of data, transform the first type ECC syndrome for the line of data to a second type ECC syndrome send a response to the master. The response includes the line of data and the second type ECC syndrome associated with the line of data.